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    CLEANING PROCESS FOR OXIDE
    11.
    发明申请
    CLEANING PROCESS FOR OXIDE 有权
    氧化物清洗工艺

    公开(公告)号：US20160126091A1

    公开(公告)日：2016-05-05

    申请号：US14532015

    申请日：2014-11-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chueh-Yang Liu ,  Neng-Hui Yang

    IPC: H01L21/02 ,  H01L21/311

    CPC classification number: H01L21/02334 ,  H01L21/0206 ,  H01L21/02181 ,  H01L21/02307 ,  H01L21/28211 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    Abstract: A cleaning process for oxide includes the following step. A substrate having a first area and a second area is provided. A first oxide layer is formed on the substrate of the first area and the second area. An ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) containing process is performed on the first oxide layer of the first area and the second area. A photoresist layer covers the first oxide layer of the first area while exposing the first oxide layer of the second area. The first oxide layer of the second area is removed. The photoresist layer is then removed.

    Abstract translation: 氧化物的清洗方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域和第二区域的基板上形成第一氧化物层。 在第一区域和第二区域的第一氧化物层上进行含有氢氧化铵（NH 4 OH）和过氧化氢（H 2 O 2）的工艺。 光致抗蚀剂层覆盖第一区域的第一氧化物层，同时暴露第二区域的第一氧化物层。 去除第二区域的第一氧化物层。 然后除去光致抗蚀剂层。

    Method of forming semiconductor device
    13.
    发明授权
    Method of forming semiconductor device 有权
    半导体器件形成方法

    公开(公告)号：US09034705B2

    公开(公告)日：2015-05-19

    申请号：US13850887

    申请日：2013-03-26

    Applicant: United Microelectronics Corp.

    Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Hsin-Kuo Hsu ,  Yu-Shu Lin ,  Szu-Hao Lai ,  Ming-Hua Chang

    IPC: H01L21/8238 ,  H01L21/8234

    CPC classification number: H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  Y10S438/938

    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

    Abstract translation: 公开了一种形成半导体器件的方法。 至少一个栅极结构设置在衬底上，其中栅极结构包括形成在栅极的侧壁上的第一间隔物。 在覆盖栅极结构的衬底上沉积第一一次性间隔物层。 第一一次性间隔物材料层被蚀刻以在第一间隔物上形成第一一次性间隔物。 在覆盖栅极结构的衬底上沉积第二一次性间隔物材料层。 蚀刻第二一次性间隔材料层以在第一一次性间隔件上形成第二一次性间隔件。 通过使用第一和第二一次性间隔件作为掩模来去除衬底的一部分，以在栅极结构旁边的衬底中形成两个凹部。 在凹部中形成应力诱导层。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING EPITAXIAL LAYER
    16.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING EPITAXIAL LAYER 有权
    半导体器件及形成外延层的方法

    公开(公告)号：US20140235038A1

    公开(公告)日：2014-08-21

    申请号：US14260294

    申请日：2014-04-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  Chin-Cheng Chien

    IPC: H01L21/02

    CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness.

    Abstract translation: 公开了一种用于形成外延层的方法。 该方法包括提供半导体衬底以及在半导体衬底中形成未掺杂的第一外延层的步骤。 优选地，半导体衬底至少包括凹部，未掺杂的第一外延层具有晶格常数，底部厚度和侧面厚度，其中晶格常数不同于半导体衬底的晶格常数，底部厚度为 基本上大于或等于侧厚度。

    MULTIGATE FIELD EFFECT TRANSISTOR AND PROCESS THEREOF
    17.
    发明申请
    MULTIGATE FIELD EFFECT TRANSISTOR AND PROCESS THEREOF 有权
    多功能场效应晶体管及其过程

    公开(公告)号：US20140117455A1

    公开(公告)日：2014-05-01

    申请号：US13662561

    申请日：2012-10-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chin-Cheng Chien ,  Chia-Lin Hsu

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L21/02225 ,  H01L21/764 ,  H01L27/11 ,  H01L29/66484 ,  H01L29/66795

    Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

    Abstract translation: 多栅场效应晶体管包括两个鳍状结构和介电层。 鳍状结构位于基底上。 电介质层覆盖基板和鳍状结构。 在两个鳍状结构之间的电介质层中至少有两个空隙。 此外，本发明还提供了一种用于形成所述多栅极场效应晶体管的多栅场效应晶体管工艺，包括以下步骤。 在基板上形成两个鳍状结构。 介电层覆盖基板和两个鳍状结构，其中在两个鳍状结构之间的电介质层中形成至少两个空隙。

    NON-PLANAR SEMICONDUCTOR STRUCTURE
    19.
    发明申请
    NON-PLANAR SEMICONDUCTOR STRUCTURE 有权
    非平面半导体结构

    公开(公告)号：US20130228836A1

    公开(公告)日：2013-09-05

    申请号：US13869037

    申请日：2013-04-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

    IPC: H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. Anon-planar semiconductor process is also provided for forming the semiconductor structure.

    Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

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