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    MRAM STRUCTURE AND METHOD OF FABRICATING THE SAME
    11.
    发明申请
    MRAM STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220246839A1

    公开(公告)日：2022-08-04

    申请号：US17725511

    申请日：2022-04-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

    IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

    Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    14.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190140074A1

    公开(公告)日：2019-05-09

    申请号：US15838243

    申请日：2017-12-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hao-Hsuan Chang ,  Yao-Hsien Chung ,  Fu-Yu Tsai

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.

    Semiconductor device and manufacturing method thereof
    15.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10283618B1

    公开(公告)日：2019-05-07

    申请号：US15838243

    申请日：2017-12-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hao-Hsuan Chang ,  Yao-Hsien Chung ,  Fu-Yu Tsai

    IPC: H01L21/338 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.

    MRAM STRUCTURE AND FABRICATING METHOD OF THE SAME
    18.
    发明申请
    MRAM STRUCTURE AND FABRICATING METHOD OF THE SAME 有权

    公开(公告)号：US20250120092A1

    公开(公告)日：2025-04-10

    申请号：US18508204

    申请日：2023-11-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai

    IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/20 ,  H10N50/85

    Abstract: An MRAM structure includes a first memory unit and a second memory unit. A conductive line is disposed between the first memory unit and the second memory unit. An SOT metal conductive line contacts and electrically connects an end of the first memory unit, an end of the conductive line and an end of the second memory unit. A first switch element is electrically connected to an end of the SOT metal conductive line, and a second switch element is electrically connected to the other end of the SOT metal conductive line. A third switch element is electrically connected to the other end of the first memory unit. A fourth switch element is electrically connected to the other end of the conductive line. A fifth switch element is electrically connected to the other end of the second memory unit.

    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    19.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权

    公开(公告)号：US20250079293A1

    公开(公告)日：2025-03-06

    申请号：US18379670

    申请日：2023-10-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tai-Cheng Hou ,  Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai

    IPC: H01L23/522 ,  H01L21/768

    Abstract: A semiconductor device and a method of fabricating the same, includes at least one dielectric layer, a conductive structure, and a first insulator. The at least one dielectric layer includes a stacked structure having a low-k dielectric layer, an etching stop layer, and a conductive layer between the low-k dielectric layer and the etching stop layer. The conductive structure is disposed in the first dielectric layer. The first insulator is disposed between the conductive layer and the conductive structure.

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