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    STRAINED SILICON STRUCTURE
    11.
    发明申请
    STRAINED SILICON STRUCTURE 有权
    应变硅结构

    公开(公告)号：US20130292775A1

    公开(公告)日：2013-11-07

    申请号：US13936214

    申请日：2013-07-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Guang-Yaw Hwang ,  Ling-Chun Chou ,  I-Chang Wang ,  Shin-Chuan Huang ,  Jiunn-Hsiung Liao ,  Shin-Chi Chen ,  Pau-Chung Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chieh-Te Chen

    IPC: H01L27/088

    CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

    Abstract translation: 应变硅衬底结构包括设置在衬底上的第一晶体管和第二晶体管。 第一晶体管包括第一栅极结构和设置在第一栅极结构的两侧的两个第一源极/漏极区域。 第一源极/漏极到栅极间距在每个第一源极/漏极区域和第一栅极结构之间。 第二晶体管包括第二栅极结构和设置在第二栅极结构的两侧的两个源极/漏极掺杂区域。 第二源极/漏极到栅极间距在每个第二源极/漏极区域和第二栅极结构之间。 第一源极/漏极到栅极距离小于第二源极/漏极到栅极距离。

    LATERAL DIFFUSION METAL-OXIDE SEMICONDUCTOR DEVICE
    12.
    发明公开
    LATERAL DIFFUSION METAL-OXIDE SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240120419A1

    公开(公告)日：2024-04-11

    申请号：US18528806

    申请日：2023-12-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ling-Chun Chou ,  Yu-Hung Chang ,  Kun-Hsien Lee

    IPC: H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/7823 ,  H01L29/0623

    Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

    Semiconductor structure and manufacturing method thereof
    13.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US10439066B2

    公开(公告)日：2019-10-08

    申请号：US15721177

    申请日：2017-09-29

    Applicant: United Microelectronics Corp.

    Inventor： Ling-Chun Chou ,  Kun-Hsien Lee

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/06

    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.

    High voltage semiconductor device
    16.
    发明授权
    High voltage semiconductor device 有权

    公开(公告)号：US11664450B2

    公开(公告)日：2023-05-30

    申请号：US17216642

    申请日：2021-03-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ling-Chun Chou ,  Te-Chi Yen ,  Yu-Hung Chang ,  Kun-Hsien Lee ,  Kai-Lin Lee

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

    CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0878

    Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

    Semiconductor structure and manufacturing method thereof
    17.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US10978589B2

    公开(公告)日：2021-04-13

    申请号：US16529523

    申请日：2019-08-01

    Applicant: United Microelectronics Corp.

    Inventor： Ling-Chun Chou ,  Kun-Hsien Lee

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165

    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.

    BIPOLAR JUNCTION TRANSISTOR
    19.
    发明申请
    BIPOLAR JUNCTION TRANSISTOR 有权

    公开(公告)号：US20180068998A1

    公开(公告)日：2018-03-08

    申请号：US15289988

    申请日：2016-10-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuan-Ti Wang ,  Ling-Chun Chou ,  Kun-Hsien Lee

    IPC: H01L27/082 ,  H01L29/06 ,  H01L27/02

    CPC classification number: H01L27/082 ,  H01L27/0207 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0813 ,  H01L29/1008 ,  H01L29/407 ,  H01L29/735

    Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.

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