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公开(公告)号：US20170084604A1
公开(公告)日：2017-03-23
申请号：US14860788
申请日：2015-09-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Pei-Shan Tseng , Yu-Cheng Liao , Ping-Chen Chang , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L27/02
CPC classification number: H01L27/0266 , H01L27/0207 , H01L27/0255 , H01L27/1203 , H01L28/00
Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.
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公开(公告)号：US09559091B2
公开(公告)日：2017-01-31
申请号：US14745458
申请日：2015-06-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Tzu Wang , Ping-Chen Chang , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L21/70 , H01L27/02 , H01L29/861 , H01L21/76 , H01L29/78 , H01L27/06 , H01L29/06 , H01L21/22 , H01L21/265 , H01L21/306 , H01L29/66 , H01L29/16 , H01L29/20
CPC classification number: H01L27/0255 , H01L21/22 , H01L21/265 , H01L21/30604 , H01L21/76 , H01L21/76224 , H01L27/0629 , H01L29/0642 , H01L29/0649 , H01L29/0657 , H01L29/0692 , H01L29/1606 , H01L29/2003 , H01L29/6609 , H01L29/66136 , H01L29/785 , H01L29/861
Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.
Abstract translation: 制造鳍式二极管结构的方法包括提供衬底，在所述衬底中形成掺杂阱，在所述掺杂阱中形成至少一个第一导电类型的掺杂区或第二掺杂型的至少一个掺杂区，执行蚀刻工艺 到所述第一导电类型的掺杂区域或第二导电类型的所述掺杂区域，以在所述第一导电类型的掺杂区域上或在所述第二导电类型的所述掺杂区域上形成多个鳍片，在所述鳍片之间形成浅沟槽隔离，并执行 对所述翅片进行掺杂工艺以形成第一导电类型的鳍片和第二导电类型的鳍片。
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公开(公告)号：US20150303183A1
公开(公告)日：2015-10-22
申请号：US14745458
申请日：2015-06-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Tzu Wang , Ping-Chen Chang , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L27/02 , H01L21/76 , H01L21/22 , H01L21/265 , H01L29/06 , H01L29/66 , H01L21/306
CPC classification number: H01L27/0255 , H01L21/22 , H01L21/265 , H01L21/30604 , H01L21/76 , H01L21/76224 , H01L27/0629 , H01L29/0642 , H01L29/0649 , H01L29/0657 , H01L29/0692 , H01L29/1606 , H01L29/2003 , H01L29/6609 , H01L29/66136 , H01L29/785 , H01L29/861
Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.
Abstract translation: 制造鳍式二极管结构的方法包括提供衬底，在所述衬底中形成掺杂阱，在所述掺杂阱中形成至少一个第一导电类型的掺杂区或第二掺杂型的至少一个掺杂区，执行蚀刻工艺 到所述第一导电类型的掺杂区域或第二导电类型的所述掺杂区域，以在所述第一导电类型的掺杂区域上或在所述第二导电类型的所述掺杂区域上形成多个鳍片，在所述鳍片之间形成浅沟槽隔离，并执行 对所述翅片进行掺杂工艺以形成第一导电类型的鳍片和第二导电类型的鳍片。
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公开(公告)号：US20150221632A1
公开(公告)日：2015-08-06
申请号：US14687921
申请日：2015-04-16
Applicant: United Microelectronics Corp.
Inventor： Chang-Tzu Wang , Ping-Chen Chang , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L27/02 , H01L29/78 , H01L27/06 , H01L29/861 , H01L29/06
CPC classification number: H01L27/0255 , H01L21/22 , H01L21/265 , H01L21/30604 , H01L21/76 , H01L21/76224 , H01L27/0629 , H01L29/0642 , H01L29/0649 , H01L29/0657 , H01L29/0692 , H01L29/1606 , H01L29/2003 , H01L29/6609 , H01L29/66136 , H01L29/785 , H01L29/861
Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.
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公开(公告)号：US08884337B2
公开(公告)日：2014-11-11
申请号：US13858927
申请日：2013-04-08
Applicant: United Microelectronics Corp.
Inventor： Chang-Tzu Wang , Ping-Chen Chang , Tien-Hao Tang
IPC: H01L27/118 , H03K3/013
CPC classification number: H03K19/00 , H01L27/0207 , H01L27/0738 , H01L27/088 , H01L27/092 , H03K19/00361
Abstract: An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor.
Abstract translation: 输出缓冲器包括输入/输出端，电压源，第一晶体管和第二晶体管。 第一晶体管包括耦合到输入/输出端的第一端，耦合到电压源的第二端和耦合到电压源的控制端。 第二晶体管包括耦合到输入/输出端的第一端，耦合到电压源的第二端和耦合到电压源的控制端。 第一晶体管的控制端和第二晶体管的控制端基本上彼此垂直，并且第一晶体管的穿通电压高于第二晶体管的穿通电压。
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Patent Agency Ranking
公开(公告)号：US10897131B2
公开(公告)日：2021-01-19
申请号：US15878421
申请日：2018-01-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Cheng Liao , Ting-Yao Lin , Ping-Chen Chang , Tien-Hao Tang
Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.
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公开(公告)号：US20200381415A1
公开(公告)日：2020-12-03
申请号：US16446599
申请日：2019-06-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ying-Wei Tseng , Chun Chiang , Ping-Chen Chang , Tien-Hao Tang
IPC: H01L27/02
Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.
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18.发明申请公开(公告)号：US20190273077A1
公开(公告)日：2019-09-05
申请号：US15927107
申请日：2018-03-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun Chiang , Ying-Wei Tseng , Ping-Chen Chang , Tien-Hao Tang
Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.
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公开(公告)号：US20180269198A1
公开(公告)日：2018-09-20
申请号：US15983113
申请日：2018-05-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Yu Huang , Kuan-Cheng Su , Tien-Hao Tang , Ping-Chen Chang
CPC classification number: H01L27/0255 , H01L27/027 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0873 , H01L29/78 , H01L29/7818 , H01L29/7831 , H01L29/7835
Abstract: An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.
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公开(公告)号：US10008489B2
公开(公告)日：2018-06-26
申请号：US14724825
申请日：2015-05-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Yu Huang , Kuan-Cheng Su , Tien-Hao Tang , Ping-Chen Chang
CPC classification number: H01L27/0255 , H01L27/027 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0873 , H01L29/78 , H01L29/7818 , H01L29/7831 , H01L29/7835
Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a gate set positioned on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the drain region, and at least a second doped region formed in the substrate. The source region and the drain region include a first conductivity type, the first doped region and the second doped region include a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other. The first doped region and the second doped region are electrically connected to each other.
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