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    METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE
    12.
    发明申请
    METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE 审中-公开
    制造非易失性存储器件的方法

    公开(公告)号：US20160172200A1

    公开(公告)日：2016-06-16

    申请号：US14569794

    申请日：2014-12-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： WEICHANG LIU ,  ZHEN CHEN ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang ,  Chih-Chien Chang

    IPC: H01L21/28

    CPC classification number: H01L29/40117 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A method for fabricating non-volatile memory device is disclosed. The method includes the steps of: providing a substrate having a stack structure thereon; performing a first oxidation process to form a first oxide layer on the substrate and the stack structure; etching the first oxide layer for forming a first spacer adjacent to the stack structure; performing a second oxidation process to form a second oxide layer on the substrate; forming a dielectric layer on the first spacer and the second oxide layer; and etching the dielectric layer for forming a second spacer.

    Abstract translation: 公开了一种用于制造非易失性存储器件的方法。 该方法包括以下步骤：提供其上具有堆叠结构的衬底; 执行第一氧化工艺以在衬底和堆叠结构上形成第一氧化物层; 蚀刻用于形成邻近堆叠结构的第一间隔物的第一氧化物层; 执行第二氧化工艺以在所述衬底上形成第二氧化物层; 在所述第一间隔物和所述第二氧化物层上形成介电层; 并蚀刻用于形成第二间隔物的电介质层。

    SEMICONDUCTOR PROCESS
    13.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20160042957A1

    公开(公告)日：2016-02-11

    申请号：US14454332

    申请日：2014-08-07

    Applicant: United Microelectronics Corp.

    Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

    IPC: H01L21/28 ,  H01L27/115 ,  H01L29/66

    CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

    Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

    Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。

    Flash cell and forming process thereof
    17.
    发明授权
    Flash cell and forming process thereof 有权
    闪电池及其成型工艺

    公开(公告)号：US09455322B1

    公开(公告)日：2016-09-27

    申请号：US14862118

    申请日：2015-09-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Weichang Liu ,  Wei Ta ,  Zhen Chen ,  Wang Xiang

    IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/788 ,  H01L27/115 ,  H01L29/51

    CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.

    Abstract translation: 闪光单元形成工艺包括以下步骤。 在基板上形成第一栅极。 第一间隔件形成在第一栅极的一侧，其中第一间隔件包括底部和顶部。 底部被去除，从而形成底切。 在第一间隔物旁边形成第一选择栅，并填入底切。 本发明还提供了一种由所述闪存单元形成工艺形成的闪光单元。 闪存单元包括第一栅极，第一间隔物和第一选择栅极。 第一栅极设置在基板上。 第一间隔件设置在第一栅极的一侧，其中第一间隔件在底部具有底切，因此露出基板。 第一选择栅设置在第一间隔物旁边并延伸到底切中。

    Semiconductor process
    18.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US09362125B2

    公开(公告)日：2016-06-07

    申请号：US14454332

    申请日：2014-08-07

    Applicant: United Microelectronics Corp.

    Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

    IPC: H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

    CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

    Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

    Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。

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