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    Multigate field effect transistor and process thereof
    11.
    发明授权
    Multigate field effect transistor and process thereof 有权
    多场效应晶体管及其工艺

    公开(公告)号：US09159831B2

    公开(公告)日：2015-10-13

    申请号：US13662561

    申请日：2012-10-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chin-Cheng Chien ,  Chia-Lin Hsu

    IPC: H01L21/70 ,  H01L29/78 ,  H01L21/764 ,  H01L29/66 ,  H01L21/02 ,  H01L27/11

    CPC classification number: H01L29/785 ,  H01L21/02225 ,  H01L21/764 ,  H01L27/11 ,  H01L29/66484 ,  H01L29/66795

    Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

    Abstract translation: 多栅场效应晶体管包括两个鳍状结构和介电层。 鳍状结构位于基底上。 电介质层覆盖基板和鳍状结构。 在两个鳍状结构之间的电介质层中至少有两个空隙。 此外，本发明还提供了一种用于形成所述多栅极场效应晶体管的多栅场效应晶体管工艺，包括以下步骤。 在基板上形成两个鳍状结构。 电介质层覆盖基板和两个鳍状结构，其中在两个鳍状结构之间的电介质层中形成至少两个空隙。

    Multi-gate field-effect transistor process
    12.
    发明授权
    Multi-gate field-effect transistor process 有权
    多栅极场效应晶体管工艺

    公开(公告)号：US08999793B2

    公开(公告)日：2015-04-07

    申请号：US14306250

    申请日：2014-06-17

    Applicant: United Microelectronics Corp.

    Inventor： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10

    CPC classification number: H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

    Abstract translation: 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从内向外减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

    METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    13.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR STRUCTURE 审中-公开
    形成半导体结构的方法

    公开(公告)号：US20150079780A1

    公开(公告)日：2015-03-19

    申请号：US14026634

    申请日：2013-09-13

    Applicant: United Microelectronics Corp.

    Inventor： Yl-Liang Liu ,  Wu-Sian Sie ,  Po-Cheng Huang ,  Chih-Hsien Chen ,  I-Lun Hung ,  Yen-Ming Chen ,  Yu-Ting Li ,  Chang-Hung Kung ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

    IPC: H01L29/66

    CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/78

    Abstract: A method of forming a semiconductor device is disclosed. A gate structure is formed on a substrate. The gate structure includes a dummy gate and a spacer at a sidewall of the dummy gate. A dielectric layer is formed on the substrate outside of the gate structure. A metal hard mask layer is formed to cover tops of the dielectric layer and the spacer and to expose a surface of the gate structure. The dummy gate is removed to form a gate trench. A low-resistivity metal layer is formed on the metal hard mask layer filling in the gate trench. The low-resistivity metal layer outside of the gate trench is removed. The metal hard mask layer is removed.

    Abstract translation: 公开了一种形成半导体器件的方法。 在基板上形成栅极结构。 栅极结构包括在虚拟栅极的侧壁处的伪栅极和间隔物。 在栅极结构外部的基板上形成电介质层。 形成金属硬掩模层以覆盖电介质层和间隔物的顶部并露出栅极结构的表面。 去除伪栅极以形成栅极沟槽。 在填充在栅极沟槽中的金属硬掩模层上形成低电阻率金属层。 除去栅极沟槽外的低电阻率金属层。 去除金属硬掩模层。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    15.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
    半导体结构及其工艺

    公开(公告)号：US20140367779A1

    公开(公告)日：2014-12-18

    申请号：US13917623

    申请日：2013-06-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

    Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a vacant part. The gate surrounds the vacant part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a vacant part in the corresponding top part, thereby forming the vacant part over a through hole. A gate is formed to surround the vacant part.

    Abstract translation: 半导体结构包括鳍状结构和栅极。 鳍状结构位于基板中，其中鳍状结构具有位于空部分正下方的通孔。 门围绕着空的部分。 此外，本发明还提供一种半导体工艺，包括用于形成所述半导体结构的以下步骤。 提供基板。 在基板上形成翅片状结构，其中，翅片状结构具有底部和顶部。 底部的一部分被去除以在相应的顶部形成空的部分，从而在通孔上形成空的部分。 形成围绕空闲部分的门。

    Semiconductor structure and process thereof
    17.
    发明授权
    Semiconductor structure and process thereof 有权
    半导体结构及其工艺

    公开(公告)号：US09401429B2

    公开(公告)日：2016-07-26

    申请号：US13917623

    申请日：2013-06-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

    Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a suspended part. The gate surrounds the suspended part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a suspended part in the corresponding top part, thereby forming the suspended part over a through hole. A gate is formed to surround the suspended part.

    Abstract translation: 半导体结构包括鳍状结构和栅极。 鳍状结构位于基板中，其中鳍状结构具有位于悬挂部分正下方的通孔。 门围绕悬挂部分。 此外，本发明还提供一种半导体工艺，包括用于形成所述半导体结构的以下步骤。 提供基板。 在基板上形成翅片状结构，其中，翅片状结构具有底部和顶部。 底部的一部分被去除以在相应的顶部部分中形成悬挂部分，从而在悬空部分上形成通孔。 形成围绕悬挂部分的门。

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    18.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权
    形成半导体结构的方法

    公开(公告)号：US20150147874A1

    公开(公告)日：2015-05-28

    申请号：US14088445

    申请日：2013-11-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Cheng Huang ,  I-Ming Tseng ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Po-Chao Tsao ,  Chien-Ting Lin ,  Shih-Fang Tzou

    IPC: H01L21/8234 ,  H01L21/265

    CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/3086 ,  H01L29/6681

    Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

    Abstract translation: 本发明提供一种用于形成半导体结构的制造方法，其中首先设置基板，在基板上设置硬掩模，然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模，然后进行图案转印处理，将翅片硬掩模和翅片硬掩模的图案转移到基板中，以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧，并进行翅片切割处理，以去除每个假翅片。

    Manufacturing method for a shallow trench isolation
    19.
    发明授权
    Manufacturing method for a shallow trench isolation 有权
    浅沟槽隔离的制造方法

    公开(公告)号：US09012300B2

    公开(公告)日：2015-04-21

    申请号：US13633104

    申请日：2012-10-01

    Applicant: United Microelectronics Corp.

    Inventor： Wu-Sian Sie ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yu-Ting Li ,  Wei-Che Tsao ,  Yen-Ming Chen ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

    IPC: H01L21/76 ,  H01L21/762

    CPC classification number: H01L21/76232 ,  H01L21/76229

    Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

    Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上顺序地形成硬掩模层和图案化的光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。

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