公开(公告)号：US11004897B2

公开(公告)日：2021-05-11

申请号：US16531108

申请日：2019-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H01L29/82 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

公开(公告)号：US09245972B2

公开(公告)日：2016-01-26

申请号：US14016393

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Yuan-Chi Pai ,  Fong-Lung Chuang

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66484 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

Abstract translation: 提供一种制造半导体器件的方法。 提供分别形成在第一区域和第二区域中的具有第一栅极和第二栅极的衬底。 在衬底上形成底层以覆盖第一区域中的第一栅极和第二区域中的第二栅极。 在第一区域中的底层上形成具有预定厚度的图案化掩模。 通过图案化掩模去除对应于第二区域中的第二栅极的底层以暴露第二栅极，其中对应于第一区域中的第一栅极的底层被部分消耗以暴露第一栅极的部分。

公开(公告)号：US20250008743A1

公开(公告)日：2025-01-02

申请号：US18885727

申请日：2024-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the first thickness is greater than the second thickness

公开(公告)号：US20230320229A1

公开(公告)日：2023-10-05

申请号：US18195383

申请日：2023-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80

CPC classification number: H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US11778922B2

公开(公告)日：2023-10-03

申请号：US17533003

申请日：2021-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L41/47 ,  H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

CPC classification number: H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

公开(公告)号：US20230200088A1

公开(公告)日：2023-06-22

申请号：US18113070

申请日：2023-02-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H10B61/00 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01F41/34 ,  G11C11/161 ,  H01F10/3254 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness

公开(公告)号：US10373861B1

公开(公告)日：2019-08-06

申请号：US16026077

申请日：2018-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ying Hsieh ,  Chih-Jung Chen ,  Chien-Hung Chen ,  Chih-Yueh Li ,  Cheng-Pu Chiu ,  Shih-Min Lu ,  Yung-Sung Lin

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

公开(公告)号：US20180226403A1

公开(公告)日：2018-08-09

申请号：US15445928

申请日：2017-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Chung Chen ,  An-Chi Liu ,  Chih-Yueh Li ,  Pei-Ching Yeh ,  Tsung-Chieh Yang

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.

公开(公告)号：US20160322299A1

公开(公告)日：2016-11-03

申请号：US14731394

申请日：2015-06-04

Applicant: United Microelectronics Corp.

Inventor： Chun-Chi Huang ,  Yung-Hung Yen ,  Hsin-Hsing Chen ,  Chih-Yueh Li ,  Tsun-Min Cheng

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first dielectric layer. The metal nitride layer is disposed in the opening. The bilayer metal layer is disposed on the metal nitride layer in the opening, where the bilayer metal layer includes a first metal layer and a second metal layer which is disposed on the first metal layer and has a greater metal concentration than that of the first metal layer. The conductive bulk layer is filled in the opening.

Abstract translation: 半导体器件包括开口，金属氮化物层，双层金属层和导电体层。 开口设置在第一电介质层中。 金属氮化物层设置在开口中。 双层金属层设置在开口中的金属氮化物层上，其中双层金属层包括第一金属层和设置在第一金属层上并且具有比第一金属的金属浓度更大的金属浓度的第二金属层 层。 导电体层填充在开口中。

公开(公告)号：US20160148878A1

公开(公告)日：2016-05-26

申请号：US14583575

申请日：2014-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Pei-Ching Yeh ,  Chih-Jen Lin

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/78

Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.

Abstract translation: 半导体图案结构包括基板，限定在基板上的输入/输出（I / O）区域，限定在基板上的芯区域，限定在基板上的虚拟区域和形成在基板上的栅电极。 在I / O区域和核心区域之间形成虚拟区域。 栅电极与I / O区域交叉并覆盖虚拟区域的一部分。