公开(公告)号：US09779942B1

公开(公告)日：2017-10-03

申请号：US15220386

申请日：2016-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31144

Abstract: A method of forming a patterned mask layer includes the following steps. A plurality of support features is formed on a mask layer. A plurality of spacers is formed on side walls of the support features. A patterned protection layer is formed on the support features and top surfaces of the spacers. At least a part of side surfaces of the spacers are not covered by the patterned protection layer, and the patterned protection layer is formed in a process environment containing methane (CH4). A trimming process is then performed to remove a part of each of the spacers. Tapered parts of the spacers may be removed by the trimming process before the step of etching the mask layer with the spacers as a mask, and the critical dimension uniformity of the patterned mask layer may be improved accordingly.

公开(公告)号：US09013024B2

公开(公告)日：2015-04-21

申请号：US14054811

申请日：2013-10-15

Applicant: United Microelectronics Corp.

Inventor： Ying-Chih Lin ,  Hsuan-Hsu Chen ,  Jiunn-Hsiung Liao ,  Lung-En Kuo

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/311 ,  H01L21/3083 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

Abstract translation: 半导体结构包括基板，凹部和材料。 凹部位于基板中，其中凹部具有上部和下部。 上部的最小宽度大于下部的最大宽度。 材料位于凹槽中。

公开(公告)号：US20140127892A1

公开(公告)日：2014-05-08

申请号：US14135520

申请日：2013-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

公开(公告)号：US20140038417A1

公开(公告)日：2014-02-06

申请号：US14054811

申请日：2013-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chih Lin ,  Hsuan-Hsu Chen ,  Jiunn-Hsiung Liao ,  Lung-En Kuo

IPC: H01L21/311

CPC classification number: H01L21/311 ,  H01L21/3083 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

Abstract translation: 半导体结构包括基板，凹部和材料。 凹部位于基板中，其中凹部具有上部和下部。 上部的最小宽度大于下部的最大宽度。 材料位于凹槽中。

公开(公告)号：US11271154B2

公开(公告)日：2022-03-08

申请号：US16529740

申请日：2019-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Ting-Hsiang Huang ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L45/00 ,  H01L43/02 ,  H01L41/297

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.

公开(公告)号：US20210296576A1

公开(公告)日：2021-09-23

申请号：US17336295

申请日：2021-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L43/12 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

公开(公告)号：US20200373479A1

公开(公告)日：2020-11-26

申请号：US16439712

申请日：2019-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Meng-Jun Wang ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L43/02 ,  H01L43/12

Abstract: A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.

公开(公告)号：US10804138B2

公开(公告)日：2020-10-13

申请号：US15712153

申请日：2017-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L21/768

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.

公开(公告)号：US09741614B1

公开(公告)日：2017-08-22

申请号：US15206330

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

Abstract: A method of forming trenches and a via by self-aligned double patterning includes providing a dielectric layer covered by an SiOC layer, a TiN layer and a SiON layer from top to bottom. At least two mandrels are formed on the SiOC layer. Later, two spacers are formed respectively at two sidewalls of each mandrel. Subsequently, the mandrels are removed. The SiOC layer and the TiN layer are patterned by using the spacers to form numerous recesses. The spacers are then removed. A mask layer with a via pattern is formed to cover the SiOC layer. A via is formed in the dielectric layer by taking the mask layer as a mask. After that, the mask layer is removed. Finally, numerous trenches are formed in the dielectric layer by taking the SiOC layer and the TiN layer as a mask.

公开(公告)号：US09023708B2

公开(公告)日：2015-05-05

申请号：US13866456

申请日：2013-04-19

Applicant: United Microelectronics Corp.

Inventor： Li-Chiang Chen ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai ,  Ching-Pin Hsu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。