公开(公告)号：US10068896B1

公开(公告)日：2018-09-04

申请号：US15445999

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Yen ,  Po-Ya Lai ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/06 ,  H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/749 ,  H01L29/66

Abstract: An ESD protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped region, and a second doped region. The well is disposed in the semiconductor substrate. The gate structure is disposed on the well. The first source/drain region and the second source/drain region are disposed in the well and disposed at two opposite sides of the gate structure respectively. The first doped region is disposed in the first source/drain region. The second doped region is disposed in the second source/drain region. A conductivity type of the first doped region is complementary to that of the first source/drain region. A conductivity type of the second doped region is complementary to that of the second source/drain region. A conductivity type of the well is complementary to that of the first source/drain region and the second source/drain region.

公开(公告)号：US10062751B2

公开(公告)日：2018-08-28

申请号：US15402204

申请日：2017-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hou-Jen Chiu ,  Ya-Ting Lin ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L29/0653 ,  H01L29/785

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

公开(公告)号：US09748222B2

公开(公告)日：2017-08-29

申请号：US15144836

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

公开(公告)号：US20170194315A1

公开(公告)日：2017-07-06

申请号：US15464362

申请日：2017-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L27/0886 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42372 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7851

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region. The gate set includes at least a first gate structure, a second gate structure, and a third gate structure.

公开(公告)号：US09691752B1

公开(公告)日：2017-06-27

申请号：US15096234

申请日：2016-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L27/0277 ,  H01L29/0619 ,  H01L29/7816

Abstract: An ESD protection device and a method of forming the same, the ESD device includes a substrate, a first doped well, a second doped well, a source and drain regions and a guard ring. The first doped well with a first conductive type is disposed in the substrate. The source and drain regions with the second conductive type are disposed in the first doped well. The guard ring with the first conductive type is also disposed in the first doped well and has a first portion extending along a first direction and a second portion extending along a second direction different from the first direction. The second doped well with the second conductive type is also disposed in the first doped well between the drain region and the second portion of the guard ring to in contact with the drain region in the first direction.

公开(公告)号：US20170125399A1

公开(公告)日：2017-05-04

申请号：US14924975

申请日：2015-10-28

Applicant: United Microelectronics Corp.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/861

Abstract: An electrostatic discharge (ESD) unit is described, including a first device, and a second device coupled to the first device in parallel. In an ESD event, the first device is turned on before the second device is turned on. The second device may be turned on by the turned-on first device to form an ESD path in the ESD event.

公开(公告)号：US09640524B2

公开(公告)日：2017-05-02

申请号：US14924708

申请日：2015-10-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L23/62 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L27/0886 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42372 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7851

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region.

公开(公告)号：US09331064B2

公开(公告)日：2016-05-03

申请号：US14742723

申请日：2015-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.

Abstract translation: 翅片二极管结构包括在衬底中形成的掺杂阱，第一导电类型的多个鳍和第二导电类型的多个翅片，其通过STI从与第一导电类型的绝缘体隔离的掺杂阱突出，至少一个掺杂区域 第一导电类型的翅片之间的衬底中的第一导电类型，STI和掺杂阱并且与第一导电类型的鳍连接并且在第二导电类型的鳍之间的衬底中的至少一个第二导电类型的掺杂区域 类型，STI和掺杂阱，并与第二导电类型的鳍连接。 第一导电类型的散热片的掺杂浓度大于其掺杂浓度大于第一导电类型的掺杂阱的第一导电类型的掺杂区域的掺杂浓度。

公开(公告)号：US20150137255A1

公开(公告)日：2015-05-21

申请号：US14082529

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L27/0277 ,  H01L27/088

Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.

Abstract translation: 描述了一种半导体器件，包括包括第一区域和第二区域的衬底，第一区域中的第一导电类型的第一MOS元件和第二区域中的第一导电类型的第二MOS元件。 第一区域比第二区域更靠近基板的拾取区域。 衬底具有第二导电类型。 第一区域中的衬底中的第一导电通路的底部深度小于第二区域中的衬底中的第二导电通路的深度。

公开(公告)号：US10672759B2

公开(公告)日：2020-06-02

申请号：US16124171

申请日：2018-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

Abstract: An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.