公开(公告)号：US20220216311A1

公开(公告)日：2022-07-07

申请号：US17178269

申请日：2021-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

IPC: H01L21/28 ,  H01L29/788 ,  H01L29/423 ,  H01L21/311 ,  H01L21/32 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/66

Abstract: A split-gate flash memory cell includes a semiconductor substrate having thereon a select gate oxide layer and a floating gate oxide layer. A floating gate is disposed on the floating gate oxide layer. A football-shaped oxide layer is disposed on the floating gate. The floating gate includes tips under the football-shaped oxide layer. A select gate is disposed on the select gate oxide layer and extended onto the football-shaped oxide layer. An inter-poly oxide layer is between the select gate and the floating gate. The inter-poly oxide layer has a thickness smaller than a thickness of the select gate oxide layer. A source region is formed in the semiconductor substrate and adjacent to the floating gate. A drain region is formed in the semiconductor substrate and adjacent to the select gate.

公开(公告)号：US20220139938A1

公开(公告)日：2022-05-05

申请号：US17103872

申请日：2020-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11558

Abstract: A semiconductor memory device includes a select transistor and a floating gate transistor on a substrate. The select transistor includes a select gate, a select gate oxide layer and a drain doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, a source doping region, a first tunnel doping region and a second tunnel doping region under the floating gate, a first tunnel oxide layer on the first tunnel doping region, and a second tunnel oxide layer on the second tunnel doping region. The floating gate oxide layer is disposed between the first tunnel oxide layer and the second tunnel oxide layer. A lightly doped diffusion region surrounds the source doping region and the second tunnel doping region.

公开(公告)号：US10468538B1

公开(公告)日：2019-11-05

申请号：US16038068

申请日：2018-07-17

Applicant: United Microelectronics Corp.

Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

IPC: H01L29/788 ,  H01L27/11517 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234

Abstract: A method for fabricating semiconductor device includes providing a substrate having a first device region and a second device region. Floating gate structure is formed in the first device region. Liner layer and nitride layer are sequentially deposited over the first device region and the second device region. The floating gate structure is conformally covered. Etching back process is performed on the nitride layer to reduce thickness of the nitride layer. The first device region is still covered by the nitride layer. A photomask layer is formed over the substrate with an opening region to expose the second device region for cleaning. The photomask layer is removed. A gate oxide layer grows on the substrate in the second device region. Anisotropic etching process is performed to remove the nitride layer, resulting in a nitride spacer on a lower portion of a sidewall of the floating gate structure.

公开(公告)号：US20190237460A1

公开(公告)日：2019-08-01

申请号：US16380953

申请日：2019-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen ,  Chien-Hung Chen

IPC: H01L27/06 ,  H01L27/11543 ,  H01L27/11541 ,  H01L29/788 ,  H01L21/285 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/31144 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; forming a floating gate on the tunnel dielectric; forming an insulation layer conformally disposed on the top surface and the sidewall surface of the floating gate; forming a control gate disposed on the insulation layer and the floating gate; and forming a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, where the spacer overlaps portions of the top surface of the floating gate

公开(公告)号：US20180294359A1

公开(公告)日：2018-10-11

申请号：US15591031

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen ,  Chien-Hung Chen

IPC: H01L29/788 ,  H01L27/11536 ,  H01L21/285 ,  H01L21/311 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L21/28273 ,  H01L21/28518 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate.

公开(公告)号：US20180114793A1

公开(公告)日：2018-04-26

申请号：US15352587

申请日：2016-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L27/11558 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66825 ,  H01L29/7883

Abstract: A single poly electrical erasable programmable read only memory (EEPROM) includes a source, a drain, a dielectric layer and an electrode layer. The source and the drain are located in a substrate, wherein the source and the drain have a first conductive type. The dielectric layer is disposed on the substrate and between the source and the drain, wherein the dielectric layer includes a first dielectric layer having two tunnel dielectric parts separating from each other, and thicknesses of the two tunnel dielectric parts are thinner than thicknesses of the other parts of the first dielectric layer. The electrode layer is disposed on the dielectric layer, wherein the electrode layer includes a first electrode disposed on the first dielectric layer, thereby the first electrode being a floating gate.

公开(公告)号：US20170018649A1

公开(公告)日：2017-01-19

申请号：US15279410

申请日：2016-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Tzu-Ping Chen

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  G11C16/14 ,  G11C16/04

CPC classification number: H01L29/7887 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.

Abstract translation: 公开了半导体器件的制造方法。 首先，提供基板，并且在基板上形成电介质堆叠，其中电介质叠层包括第一氧化硅层和第一氮化硅层。 接下来，对电介质堆叠进行构图，去除第一氮化硅层的一部分以在第一氮化硅层的两端形成两个凹部，在两个凹部中形成第二氧化硅层，在第二硅上形成间隔物 氧化物层和与第二氧化硅层相邻的第三氧化硅层。

公开(公告)号：US09349815B2

公开(公告)日：2016-05-24

申请号：US14488295

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Yi Tseng ,  Tzu-Ping Chen ,  Chun-Lung Chang ,  Chih-Haw Lee ,  Wei-Shiang Huang ,  Chien-Hung Chen

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42368 ,  H01L21/28035 ,  H01L21/28158 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.

Abstract translation: 提供了栅极结构。 栅极结构包括衬底，设置在衬底上的栅极和设置在衬底和栅极之间的栅极电介质层，其中栅极电介质层为杠铃形状。 杠铃具有连接到两个凸起端的薄中心。 凸出部分的一部分延伸到栅极和衬底中。

公开(公告)号：US11515316B2

公开(公告)日：2022-11-29

申请号：US17103872

申请日：2020-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen

IPC: H01L27/11524 ,  H01L27/11558 ,  H01L27/11519

Abstract: A semiconductor memory device includes a select transistor and a floating gate transistor on a substrate. The select transistor includes a select gate, a select gate oxide layer and a drain doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, a source doping region, a first tunnel doping region and a second tunnel doping region under the floating gate, a first tunnel oxide layer on the first tunnel doping region, and a second tunnel oxide layer on the second tunnel doping region. The floating gate oxide layer is disposed between the first tunnel oxide layer and the second tunnel oxide layer. A lightly doped diffusion region surrounds the source doping region and the second tunnel doping region.

公开(公告)号：US10332875B2

公开(公告)日：2019-06-25

申请号：US15591031

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen ,  Chien-Hung Chen

IPC: H01L29/788 ,  H01L27/06 ,  H01L21/285 ,  H01L21/311 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11541 ,  H01L27/11543

Abstract: A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate.