公开(公告)号：US09754943B1

公开(公告)日：2017-09-05

申请号：US15272425

申请日：2016-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kai-Jiun Chang ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Wei-Hsin Liu ,  Jui-Min Lee ,  Chia-Lung Chang

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L27/10808 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/53295 ,  H01L27/10823 ,  H01L27/10876

Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural word lines and plural bit lines. The word lines are disposed in the substrate along a first trench extending along a first direction. Each of the word lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes TiSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof. The bit lines are disposed over the word lines and extended along a second direction across the first direction.

公开(公告)号：US20160379864A1

公开(公告)日：2016-12-29

申请号：US15259041

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/32 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/76825 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 半导体工艺包括以下步骤。 金属图案形成在第一电介质层上。 形成可修饰层以覆盖金属图案和第一介电层。 执行修改处理以修改金属图案的顶侧上的可修改层的一部分，从而形成顶部掩模。 执行去除过程以去除金属图案的侧壁上的可修饰层的一部分，但保留顶部掩模。 形成在顶部掩模之下和金属图案之间具有空隙的电介质层。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US10672864B2

公开(公告)日：2020-06-02

申请号：US16297733

申请日：2019-03-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L29/94 ,  H01L27/108

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US10453677B2

公开(公告)日：2019-10-22

申请号：US15644821

申请日：2017-07-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Cheng-Hsu Huang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Shih-Fang Tzou

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L27/108

Abstract: A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H2O2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.

公开(公告)号：US20190221571A1

公开(公告)日：2019-07-18

申请号：US15885729

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Hsin Liu ,  Cheng-Hsu Huang ,  Jui-Min Lee ,  Yi-Wei Chen

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/10894 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10897

Abstract: A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.

公开(公告)号：US20190172722A1

公开(公告)日：2019-06-06

申请号：US16158316

申请日：2018-10-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Wei-Hsin Liu ,  Ying-Chih Lin ,  Jui-Min Lee ,  Gang-Yi Lin ,  Fu-Che Lee

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L27/105

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1052

Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.

公开(公告)号：US10312080B2

公开(公告)日：2019-06-04

申请号：US15859750

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Ching-Hsiang Chang ,  Jui-Min Lee ,  Chia-Lung Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L21/02

Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.

公开(公告)号：US20180366323A1

公开(公告)日：2018-12-20

申请号：US15644821

申请日：2017-07-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Cheng-Hsu Huang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Shih-Fang Tzou

IPC: H01L21/02 ,  H01L21/762 ,  H01L27/108

CPC classification number: H01L21/02282 ,  H01L21/0206 ,  H01L21/02307 ,  H01L21/02312 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/76229 ,  H01L21/76237 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H2O2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.

公开(公告)号：US20180308923A1

公开(公告)日：2018-10-25

申请号：US15927103

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L28/82 ,  H01L27/10808 ,  H01L27/10855 ,  H01L28/87 ,  H01L29/94

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US09543195B1

公开(公告)日：2017-01-10

申请号：US15259041

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/32

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/76825 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 半导体工艺包括以下步骤。 金属图案形成在第一电介质层上。 形成可修饰层以覆盖金属图案和第一介电层。 执行修改处理以修改金属图案的顶侧上的可修改层的一部分，从而形成顶部掩模。 执行去除过程以去除金属图案的侧壁上的可修饰层的一部分，但保留顶部掩模。 形成在顶部掩模之下和金属图案之间具有空隙的电介质层。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。