公开(公告)号：US10103034B2

公开(公告)日：2018-10-16

申请号：US15678134

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/78

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US20180012772A1

公开(公告)日：2018-01-11

申请号：US15678134

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US09673053B2

公开(公告)日：2017-06-06

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

公开(公告)号：US09466535B2

公开(公告)日：2016-10-11

申请号：US14636940

申请日：2015-03-03

Applicant: United Microelectronics Corp.

Inventor： Po-Cheng Huang ,  Kun-Ju Li ,  Yu-Ting Li ,  Chih-Hsun Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/306

CPC classification number: H01L21/823437 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.

Abstract translation: 公开了形成目标图案的方法。 提供具有多个散热片的基板。 在鳍片和非目标区域的至少一部分中形成多个掩模图案。 目标图案分别形成在掩模图案之间的沟槽中。 去除掩模图案。 利用所公开的方法，可以以基本相等的厚度形成目标图案。 在目标图案是伪栅极的情况下，在虚拟栅极去除步骤中没有观察到由不均匀厚度引起的诸如伪栅极残留或栅极沟槽加宽的常规缺陷。

公开(公告)号：US20160260637A1

公开(公告)日：2016-09-08

申请号：US14636940

申请日：2015-03-03

Applicant: United Microelectronics Corp.

Inventor： Po-Cheng Huang ,  Kun-Ju Li ,  Yu-Ting Li ,  Chih-Hsun Lin

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.

Abstract translation: 公开了形成目标图案的方法。 提供具有多个散热片的基板。 在鳍片和非目标区域的至少一部分中形成多个掩模图案。 目标图案分别形成在掩模图案之间的沟槽中。 去除掩模图案。 利用所公开的方法，可以以基本相等的厚度形成目标图案。 在目标图案是伪栅极的情况下，在虚拟栅极去除步骤中没有观察到由不均匀厚度引起的诸如伪栅极残留或栅极沟槽加宽的常规缺陷。

公开(公告)号：US20160013100A1

公开(公告)日：2016-01-14

申请号：US14461433

申请日：2014-08-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Po-Cheng Huang ,  Chih-Chien Liu ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chang-Hung Kung ,  Wen-Chin Lin ,  Chih-Hsun Lin ,  Kuo-Chin Hung

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/32136 ,  H01L21/3215 ,  H01L21/76859 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A via structure and a method of forming the same are provided. In the forming method of the present invention, a via is formed in a dielectric layer. Next, a U-shaped seed layer is formed in the via. After that, a conductive material is selectively formed in the via to form a conductive bulk layer in the via. Through the present invention, the purposes of effectively removing the overhang adjacent to the opening of the via and protecting the U-shaped seed layer in the via can be achieved.

Abstract translation: 提供通孔结构及其形成方法。 在本发明的形成方法中，在电介质层中形成通孔。 接下来，在通孔中形成U形种子层。 之后，在通路中选择性地形成导电材料，以在通孔中形成导电体层。 通过本发明，可以实现有效地去除邻近通孔开口的突出端并保护通孔中的U形种子层的目的。

公开(公告)号：US09093465B2

公开(公告)日：2015-07-28

申请号：US14102515

申请日：2013-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ting Li ,  Po-Cheng Huang ,  Wu-Sian Sie ,  Chun-Hsiung Wang ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Rai-Min Huang

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/02112 ,  H01L21/02318 ,  H01L21/32055 ,  H01L21/3212 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少包括翅片结构的基板，并且形成材料层以覆盖翅片结构。 然后，在材料层上进行第一平面化处理以形成第一材料层，并且在第一材料层上形成氧化物层。 随后，完全除去氧化物层以露出第一材料层，并且在完全除去氧化物层之后，在第一材料层上原位形成第二材料层。

公开(公告)号：US20150140819A1

公开(公告)日：2015-05-21

申请号：US14083456

申请日：2013-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  I-Ming Tseng

IPC: H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/31053 ,  H01L21/76224

Abstract: A semiconductor process includes the following steps. A substrate having trenches with different sizes is provided. A first oxide layer is formed to entirely cover the substrate. A prevention layer is formed on the first oxide layer. A first filling layer is formed on the prevention layer and fills the trenches until the first filling layer is higher than the substrate. A first polishing process is performed to polish the first filling layer until exposing the prevention layer. A second polishing process is performed to polish the first filling layer, the prevention layer and the first oxide layer until the substrate is exposed.

Abstract translation: 半导体工艺包括以下步骤。 提供具有不同尺寸的沟槽的衬底。 形成第一氧化物层以完全覆盖衬底。 在第一氧化物层上形成防止层。 第一填充层形成在预防层上并填充沟槽直到第一填充层高于衬底。 执行第一抛光处理以抛光第一填充层直到暴露预防层。 进行第二抛光处理以抛光第一填充层，防止层和第一氧化物层，直到基板被暴露。

公开(公告)号：US20190035794A1

公开(公告)日：2019-01-31

申请号：US16151323

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/108

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US20180061656A1

公开(公告)日：2018-03-01

申请号：US15245194

申请日：2016-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC: H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/31055 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/823431

Abstract: A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.