公开(公告)号：US09443842B2

公开(公告)日：2016-09-13

申请号：US14926851

申请日：2015-10-29

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee ,  Yin-Ku Chang

IPC: H01L27/02 ,  H01L27/07 ,  H01L49/02 ,  H01L23/528 ,  H01L27/06 ,  H01L29/93 ,  H01L29/94 ,  H01L23/522 ,  H01L27/08

CPC classification number: H01L27/0288 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0641 ,  H01L27/0788 ,  H01L27/0805 ,  H01L28/10 ,  H01L28/40 ,  H01L28/60 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern, and the second metal pattern. The third metal pattern is electrically grounded. An inductor is disposed over the third metal pattern.

Abstract translation: 本发明提供一种集成电路装置。 集成电路装置包括基板。 第一电容器设置在基板上。 第一金属图案耦合到第一电容器的第一电极。 第二金属图案耦合到第二电容器的第一电极。 第三金属图案设置在第一和第二金属图案之上。 第三金属图案覆盖第一电容器，第一金属图案和第二金属图案。 第三金属图案电接地。 电感器设置在第三金属图案之上。

公开(公告)号：US20160079694A1

公开(公告)日：2016-03-17

申请号：US14551094

申请日：2014-11-24

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H01R12/77

CPC classification number: H01R12/771 ,  H01R13/6471 ,  H01R13/6473 ,  H05K1/025 ,  H05K1/117 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/09781 ,  H05K2201/10189

Abstract: A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.

Abstract translation: 提供一种适于FPC连接器的插脚布置。 引脚布置包括引脚通道。 引脚通道包括一对接地引脚，一对差分引脚和至少一个未连接（NC）引脚。 差分引脚位于一对接地引脚之间。 所述至少一个NC销位于所述一对差动销之间，或位于所述一对接地引脚中的一个与所述一对接地引脚中的一个与其相邻的所述一对差动引脚之一中。 通过在所述一对差动引脚之间和/或差分引脚和与其相邻的接地引脚之间增加至少一个NC引脚，所述一对差动引脚和/或差分引脚与接地引脚之间的距离 因此增加了一对差分引脚的差分特性阻抗，以减少阻抗失配的影响。

公开(公告)号：US09703343B2

公开(公告)日：2017-07-11

申请号：US14046629

申请日：2013-10-04

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee

IPC: G06F1/26 ,  G06F1/16

CPC classification number: G06F1/266 ,  G06F1/1632

Abstract: A transmittal system including an extension device, a connection device, and an impedance device is disclosed. The extension device includes a first connection port and is coupled to a peripheral device. The connection device includes a second connection port and a third connection port. The second connection port is coupled to the first connection port. The third connection port is coupled to an electronic device. The impedance device connects at least one of the first, the second and the third connection ports to ground.

公开(公告)号：US09443843B2

公开(公告)日：2016-09-13

申请号：US14926888

申请日：2015-10-29

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee ,  Yin-Ku Chang

IPC: H01L27/02 ,  H01L27/07 ,  H01L49/02 ,  H01L23/528 ,  H01L27/06 ,  H01L29/93 ,  H01L29/94 ,  H01L23/522 ,  H01L27/08

CPC classification number: H01L27/0288 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0641 ,  H01L27/0788 ,  H01L27/0805 ,  H01L28/10 ,  H01L28/40 ,  H01L28/60 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern and the second metal pattern. The third metal pattern is electrically grounding. An inductor is disposed over the third metal pattern.

Abstract translation: 本发明提供一种集成电路装置。 集成电路装置包括基板。 第一电容器设置在基板上。 第一金属图案耦合到第一电容器的第一电极。 第二金属图案耦合到第二电容器的第一电极。 第三金属图案设置在第一和第二金属图案之上。 第三金属图案覆盖第一电容器，第一金属图案和第二金属图案。 第三金属图案是电接地。 电感器设置在第三金属图案之上。

公开(公告)号：US09338879B2

公开(公告)日：2016-05-10

申请号：US14534170

申请日：2014-11-06

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K1/182 ,  H05K2201/042 ,  H05K2201/10189

Abstract: A through-hole layout structure is suitable for a circuit board. The through-hole layout structure includes a pair of first differential through-holes, a pair of second differential through-holes, a first ground through-hole, a second ground through-hole, and a third ground through-hole, which are all arranged on a first line. The first ground through-hole is located between the pair of first differential through-holes and the pair of second differential through-holes. The pair of first differential through-holes is located between the first ground through-hole and the second ground through-hole. The pair of second differential through-holes is located between the first ground through-hole and the third ground through-hole.

Abstract translation: 通孔布局结构适用于电路板。 通孔布局结构包括一对第一差分通孔，一对第二差分通孔，第一接地通孔，第二接地通孔和第三接地通孔，这些都是 安排在第一行。 第一接地通孔位于一对第一差分通孔和一对第二差动通孔之间。 一对第一差分通孔位于第一接地通孔和第二接地通孔之间。 一对第二差分通孔位于第一接地通孔和第三接地通孔之间。

公开(公告)号：US09210800B1

公开(公告)日：2015-12-08

申请号：US14533098

申请日：2014-11-05

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01P3/08

CPC classification number: H05K1/0245 ,  H01P3/026 ,  H01P3/08 ,  H05K1/0224 ,  H05K2201/09336 ,  H05K2201/09618

Abstract: A circuit layout structure is suitable for a circuit board and includes following components. A first differential pair and a second differential pair respectively extend from the inside of a chip area of the circuit board to the outside of the chip area through a first patterned conductive layer of the circuit board, and respectively extend between the chip area and a port area of the circuit board through a second patterned conductive layer of the circuit board. A third differential pair extends from the chip area to the port area through the first patterned conductive layer. A first ground plane is constituted by the first patterned conductive layer. Orthogonal projections of the first differential pair and the second differential pair on the second patterned conductive layer overlap the first ground plane.

Abstract translation: 电路布局结构适用于电路板，并包括以下部件。 第一差分对和第二差分对分别从电路板的芯片区域的内部经由电路板的第一图案化导电层延伸到芯片区域的外部，并且分别在芯片区域和端口之间延伸 通过电路板的第二图案化导电层的电路板的面积。 第三差分对通过第一图案化导电层从芯片区域延伸到端口区域。 第一接地层由第一图案化导电层构成。 第二图案化导电层上的第一差分对和第二差分对的正交投影与第一接地平面重叠。