LATTICE MISMATCHED HETEROJUNCTION STRUCTURES AND DEVICES MADE THEREFROM
    11.
    发明申请
    LATTICE MISMATCHED HETEROJUNCTION STRUCTURES AND DEVICES MADE THEREFROM 有权
    小型异构异构结构及其设备

    公开(公告)号:US20140264375A1

    公开(公告)日:2014-09-18

    申请号:US13831449

    申请日:2013-03-14

    Abstract: Semiconductor heterojunction structures comprising lattice mismatched, single-crystalline semiconductor materials and methods of fabricating the heterojunction structures are provided. The heterojunction structures comprise at least one three-layer junction comprising two layers of single-crystalline semiconductor and a current tunneling layer sandwiched between and separating the two layers of single-crystalline semiconductor material. Also provided are devices incorporating the heterojunction structures, methods of making the devices and method of using the devices.

    Abstract translation: 提供包括晶格失配的单晶半导体材料和制造异质结结构的方法的半导体异质结结构。 异质结结构包括至少一个三层结,其包含两层单晶半导体和夹在两层单晶半导体材料之间并分离两层单晶半导体材料的电流隧穿层。 还提供了结合异质结结构的器件,制造器件的方法和使用器件的方法。

    Doped and strained flexible thin-film transistors
    20.
    发明授权
    Doped and strained flexible thin-film transistors 有权
    掺杂和应变柔性薄膜晶体管

    公开(公告)号:US09006785B2

    公开(公告)日:2015-04-14

    申请号:US13751477

    申请日:2013-01-28

    Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.

    Abstract translation: 提供掺杂和应变的半导体三层结构。 还提供了机械灵活的晶体管,包括射频晶体管,结合三层结构和制造三层结构和晶体管的方法。 三层结构包括第一层单晶半导体材料,第二层单晶半导体材料和第三层单晶半导体材料。 在结构中,第二层与第一和第三层接触并夹在第一和第三层之间,并且第一层被选择性地掺杂以在该层中提供一个或多个掺杂区域。

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