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18 条记录 (耗时 0.02 秒)

    Electronic device package with enhanced heat dissipation effect
    14.
    发明授权
    Electronic device package with enhanced heat dissipation effect 失效
    电子器件封装具有增强的散热效果

    公开(公告)号：US06236567B1

    公开(公告)日：2001-05-22

    申请号：US09453301

    申请日：1999-12-03

    申请人： Shih-Li Chen

    发明人： Shih-Li Chen

    IPC分类号： H05K720

    CPC分类号： H01L23/36 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

    摘要： An electronic device package with enhanced heat dissipation effect comprises a lead frame and an outer frame with electrically insulating surface. The outer frame encloses the electronic device with a predetermined gap therebetween. The lead frame has a plurality of inner leads extending to the upper surface of the electronic device and a plurality of outer leads enclosing the outer surface of the outer frame. Each inner lead and each outer lead are linked by a slanting portion. The plurality of outer leads includes at least one ground outer lead with larger cross section area than other outer leads. Therefore, the heat generated by the electronic device can be conducted outside through the ground outer lead when the ground outer lead is connected to other device.

    摘要翻译： 具有增强的散热效果的电子器件封装包括引线框架和具有电绝缘表面的外框架。 外框围住电子设备，其间具有预定的间隙。 引线框架具有延伸到电子设备的上表面的多个内引线和包围外框的外表面的多个外引线。 每个内部引线和每个外部引线通过倾斜部分连接。 多个外引线包括至少一个接地外引线，其横截面面积大于其它外引线。 因此，当将外部引线连接到其他设备时，电子设备产生的热量可以通过接地外部引线向外部传导。

    Indicating adhesion status between substrate and encapsulant of a packaged electronic device
    15.
    发明授权
    Indicating adhesion status between substrate and encapsulant of a packaged electronic device 失效
    指示封装的电子设备的衬底和密封剂之间的粘附状态

    公开(公告)号：US6068129A

    公开(公告)日：2000-05-30

    申请号：US184262

    申请日：1998-11-02

    申请人： Shih-Li Chen

    发明人： Shih-Li Chen

    IPC分类号： B65D79/02 ,  B65D85/00

    CPC分类号： B65D79/02

    摘要： An indicator based on the present invention for indicating the adhesion status between a substrate and the encapsulation layer of a packaged electronic device is characterized in that at least one indicating pattern and one indicating region surrounding the indicating pattern are formed on the substrate, the adhesion between the indicating pattern and the encapsulant is very good while that between the indicating region and the encapsulant is relatively poor, both the indicating pattern and the indicating region are covered by molding encapsulant which is stripped off when having become hardening, thereby the status of the indicating pattern appearing after stripping off the encapsulant can indicate the adhesion quality (integration quality) between the encapsulation layer and the substrate. The indicator realizes a non-destructive quality checking process in which each electronic device can be checked to achieve one hundred percent of quality control.

    摘要翻译： 基于本发明的用于指示衬底和封装电子器件的封装层之间的粘附状态的指示器的特征在于，在衬底上形成至少一个指示图案和围绕指示图案的指示区域， 指示图案和密封剂非常好，而指示区域和密封剂之间相对较差，指示图案和指示区域都被成型密封剂覆盖，该密封剂在变硬时被剥离，因此指示状态 剥离密封剂后出现的图案可以表示封装层和基材之间的粘合质量（整合质量）。 该指标实现了无损检测过程，其中可以检查每个电子设备以达到百分之百的质量控制。

    Method of connecting TEHS on PBGA and modified connecting structure
    16.
    发明授权
    Method of connecting TEHS on PBGA and modified connecting structure 失效
    在PBGA上连接TEHS的方法和改进的连接结构

    公开(公告)号：US5851337A

    公开(公告)日：1998-12-22

    申请号：US885343

    申请日：1997-06-30

    申请人： Shih-Li Chen

    发明人： Shih-Li Chen

    IPC分类号： H01L23/31 ,  H01L23/34 ,  H01L23/433 ,  B32B31/00

    CPC分类号： H01L23/34 ,  H01L23/3128 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/15311

    摘要： A method for connecting TEHS to PBGA and a modified connecting structure for TEHS and PBGA are disclosed. The structure improves both heat dissipation efficiency of PBGA by TEHS with high heat conductivity and electrical performance of PBGA by TEHS which is electrically connected to the circuit in PBGA substrate. There are two methods of connecting TEHS to PBGA, including metallic soldering and nonmetallic adhesion. In the metallic soldering, the contact region of the TEHS is covered with a layer of solder tin and soldered to metallic contact region of the growing circuit in the substrate. In the nonmetallic adhesion, the metallic contact region of the growing circuit is covered with a layer of conductive resin. The TEHS is adhered and fixed to the metallic region by curing the conductive resin. Such two methods achieve that the TEHS is completely connected to the ground circuit in the substrate and the inductance of the whole device is reduced to decrease the noise which is generated by the inductance, and further to improve the quality of high speed transmission. Modified structures for soldering TEHS are also provided to reduce the concentration of stress.

    摘要翻译： 公开了一种用于将TEHS连接到PBGA的方法和用于TEHS和PBGA的改进的连接结构。 该结构通过TEHS具有高导热性的PBGA和通过TEHS电连接到PBGA基板中的电路的TEHS的电性能来提高散热效率。 连接TEHS与PBGA有两种方法，包括金属焊接和非金属粘附。 在金属焊接中，TEHS的接触区域覆盖有一层焊锡，并焊接到衬底中生长电路的金属接触区域。 在非金属粘合中，生长电路的金属接触区域覆盖有导电树脂层。 通过固化导电树脂将TEHS粘附并固定到金属区域。 这两种方法实现了TEHS完全连接到衬底中的接地电路，并且整个器件的电感被减小以降低由电感产生的噪声，并且进一步提高高速传输的质量。 还提供用于焊接TEHS的改进结构以减少应力集中。

    Process for releasing a runner from an electronic device package on a laminate plate
    17.
    发明授权
    Process for releasing a runner from an electronic device package on a laminate plate 失效
    用于从层压板上的电子装置封装中释放流道的工艺

    公开(公告)号：US06096250A

    公开(公告)日：2000-08-01

    申请号：US36093

    申请日：1998-03-06

    申请人： Shih-Li Chen

    发明人： Shih-Li Chen

    IPC分类号： B29C37/02 ,  B29C45/14 ,  H01L21/56

    CPC分类号： H01L21/565 ,  B29C37/02 ,  B29C45/14655 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311

    摘要： A process for releasing a runner or gate from an electronic device on a laminate plate after molding process is included. The area of the laminate plate designed to be covered with molding compound is cleaned in advance by appropriate physical and chemical process to enhance the adhesion property, and the area to be covered by the runner or gate is protected from the cleaning process to maintain the original property of low adhesion to the laminate plate. The runner or gate can be easily released from the laminate plate without damage to the molding compound after the molding process, and the yield of the electronic device is increased.

    摘要翻译： 包括在模制过程之后从层压板上的电子设备释放流道或浇口的工艺。 预先通过适当的物理和化学过程清洁设计成被模塑料覆盖的层压板的面积，以提高粘附性，并且防止由浇道或浇口覆盖的区域进行清洁处理以保持原始 对层压板的粘附性低的特性。 浇铸或浇口可以容易地从层压板上脱模而不会在模制过程之后损坏模塑料，并且电子装置的产量增加。

    Chip scale package
    18.
    发明授权
    Chip scale package 失效
    芯片级封装

    公开(公告)号：US6087586A

    公开(公告)日：2000-07-11

    申请号：US55750

    申请日：1998-04-07

    申请人： Shih-Li Chen

    发明人： Shih-Li Chen

    IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/48

    CPC分类号： H01L23/4951 ,  H01L23/3157 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01079 ,  H01L2924/14

    摘要： A chip scale package for packaging an IC chip includes a package frame displaced from the side and bottom surfaces of the IC chip by a predetermined gap and a pair of leads symmetrically extending in opposite directions. Each lead has an inner lead portion coupled to a bonding point on the top surface of the IC chip, and an outer lead portion bent and contoured in such a way that to follow the shape of the outside surface of the package frame. The lead further includes a connecting segment extending between the inner lead portion and the outer lead portion. Under heat induced stress, an angle between the connecting segment and the wall of the package frame changes causing displacement of the IC chip from its original position, and the gap between the surfaces of the IC chip and the package frame absorbs deviations in position of the IC chip, to cushion the stress effect.

    摘要翻译： 用于封装IC芯片的芯片级封装包括从IC芯片的侧表面和底表面以预定间隙移位的封装框架和一对沿着相反方向延伸的引线。 每个引线具有耦合到IC芯片的顶表面上的接合点的内引线部分和弯曲和成形的外引线部分，使得能够跟随封装框架的外表面的形状。 引线还包括在内引线部分和外引线部分之间延伸的连接段。 在热诱导应力下，连接段和封装框架的壁之间的角度改变导致IC芯片从其初始位置的位移，并且IC芯片和封装框架的表面之间的间隙吸收了 IC芯片，缓冲应力效应。