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11.发明授权公开(公告)号：US07984409B2
公开(公告)日：2011-07-19
申请号：US11875193
申请日：2007-10-19
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L21/76885
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure comprises an insulating layer of a dielectric material, an opening having sidewalls extending from a top surface of the insulating layer toward a bottom surface of the insulating layer, and a conductive feature disposed in the opening. The design structure includes a top capping layer disposed on at least a top surface of the conductive feature and a conductive liner layer disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer of the design structure has sidewall portions that project above the top surface of the insulating layer adjacent to the sidewalls of the opening.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括介电材料的绝缘层，具有从绝缘层的顶表面朝向绝缘层的底表面延伸的侧壁的开口以及设置在该开口中的导电特征。 该设计结构包括设置在导电特征的至少顶表面上的顶盖层和至少沿开口的侧壁设置在绝缘层和导电特征之间的导电衬垫层。 该设计结构的导电衬里层具有侧壁部分，该侧壁部分突出在邻近开口侧壁的绝缘层顶表面上方。
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12.发明授权Interconnect structures with improved electromigration resistance and methods for forming such interconnect structures 有权具有改进的电迁移电阻的互连结构和用于形成这种互连结构的方法公开(公告)号：US07666781B2
公开(公告)日：2010-02-23
申请号：US11562550
申请日：2006-11-22
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L21/76885
摘要： Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric material having a top surface and a bottom surface between the top surface and a substrate. An opening, such as a trench, has sidewalls extending from the top surface of the insulating layer toward the bottom surface and is at least partially filled by a conductive feature. A capping layer is disposed on at least a top surface of the conductive feature. A conductive liner layer is disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer has sidewall portions projecting above the top surface of the insulating layer adjacent to the sidewalls of the opening.
摘要翻译： 互连结构包括与至少相邻绝缘层非平面的衬里层和在绝缘层中嵌入的导电特征上的至少一个覆盖层。 互连结构包括具有上表面和顶表面与基底之间的底表面的电介质材料的绝缘层。 诸如沟槽的开口具有从绝缘层的顶表面朝向底表面延伸并且至少部分地被导电特征填充的侧壁。 覆盖层设置在导电特征的至少顶表面上。 导电衬垫层至少沿着开口的侧壁设置在绝缘层和导电特征之间。 导电衬垫层具有在与开口的侧壁相邻的绝缘层的顶表面上方突出的侧壁部分。
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13.发明申请公开(公告)号：US20090001477A1
公开(公告)日：2009-01-01
申请号：US11770798
申请日：2007-06-29
IPC分类号： H01L29/78 , H01L21/8232
CPC分类号： H01L21/28052 , H01L21/28097 , H01L21/823443 , H01L21/82345 , H01L29/4933 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： Embodiments of the invention generally relate to semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers.
摘要翻译： 本发明的实施例一般涉及半导体器件，更具体地涉及形成部分硅化和完全硅化结构。 制造部分硅化和完全硅化的结构可能涉及创建一个或多个栅极叠层。 可以暴露第一栅极叠层的多晶硅层，并且可以在其上沉积第一金属层以产生部分硅化结构。 此后，可以暴露第二栅极堆叠的多晶硅层，并且可以在其上沉积第二金属层以形成完全硅化的结构。 在一些实施例中，可以不暴露一个或多个栅极叠层的多晶硅层，并且可以用非硅化多晶硅层形成电阻器。
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14.发明申请Interconnect Structures with Liner Repair Layers and Methods for Forming Such Interconnection Structures 有权具有衬管修复层的互连结构和形成这种互连结构的方法公开(公告)号：US20080122090A1
公开(公告)日：2008-05-29
申请号：US11468392
申请日：2006-08-30
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
摘要翻译： 互连结构包括在绝缘层中形成在粗糙化介电材料上的衬垫中桥接破裂的共形衬里修复层以及形成这种互连结构的方法。 保形衬里修复层由诸如含钴材料的导电材料形成。 保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。
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公开(公告)号：US20120248567A1
公开(公告)日：2012-10-04
申请号：US13494327
申请日：2012-06-12
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.
摘要翻译： 一个结构。 该结构包括：衬底，衬底中的第一电极，衬底和第一电极上的第一电介质层，第一电介质层上方的第二电介质层和埋在第一电介质层中的熔丝元件。 第一电极包括第一导电材料。 第一电介质层的顶表面比第一电介质层的任何其它表面更远离第一电极的顶表面。 第一电介质层包括第一电介质材料和第二电介质材料。 第二电介质层的底表面与第一电介质层的顶表面直接物理接触。 第二电介质层包括第二电介质材料。
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公开(公告)号：US07968949B2
公开(公告)日：2011-06-28
申请号：US11668717
申请日：2007-01-30
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76829 , H01L21/76831 , H01L29/6653 , H01L29/78
摘要： Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer to the first liner; forming a second liner in the contact hole including over the first liner covering the sidewall; removing the first and second liners at a bottom of the contact hole; and filling the contact hole with a conductive material to form the contact. The thicker liner(s) over the sidewall of the structure prevents shorting, and allows for at least maintaining any intrinsic stress in one or more of the liner(s).
摘要翻译： 公开了触点形成方法和相关的半导体器件。 一种方法包括在结构和衬底上形成第一衬里，第一衬套覆盖结构的侧壁; 在所述第一衬垫和所述结构上形成介电层; 在所述介电层中形成与所述第一衬垫的接触孔; 在所述接触孔中形成第二衬垫，包括覆盖所述侧壁的所述第一衬套上方; 在接触孔的底部移除第一和第二衬垫; 并用导电材料填充接触孔以形成接触。 结构侧壁上较厚的衬套防止短路，并允许至少保持一个或多个衬套中的任何固有应力。
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17.发明授权Design structures incorporating interconnect structures with liner repair layers 有权设计结构包括具有衬里修复层的互连结构公开(公告)号：US07494916B2
公开(公告)日：2009-02-24
申请号：US11875345
申请日：2007-10-19
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes an interconnect structure with a liner formed on roughened dielectric material in an insulating layer and a conformal liner repair layer bridging that breaches in the liner. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括互连结构，其具有在绝缘层中的粗糙化介电材料上形成的衬垫和桥接该衬里中的破损的保形衬里修复层。 保形衬里修复层由诸如含钴材料的导电材料形成。 保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。
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18.发明申请公开(公告)号：US20090007037A1
公开(公告)日：2009-01-01
申请号：US11925413
申请日：2007-10-26
IPC分类号： G06F9/45
CPC分类号： H01L21/28052 , H01L21/28097 , H01L21/823443 , H01L21/82345 , H01L21/823475 , H01L21/823835 , H01L21/823842 , H01L21/823871 , H01L28/20 , H01L29/4933 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers.
摘要翻译： 本发明的实施例一般涉及用于半导体器件的方法，系统和设计结构，更具体地涉及形成部分硅化和完全硅化结构。 制造部分硅化和完全硅化的结构可能涉及创建一个或多个栅极叠层。 可以暴露第一栅极叠层的多晶硅层，并且可以在其上沉积第一金属层以产生部分硅化结构。 此后，可以暴露第二栅极堆叠的多晶硅层，并且可以在其上沉积第二金属层以形成完全硅化的结构。 在一些实施例中，可以不暴露一个或多个栅极叠层的多晶硅层，并且可以用非硅化多晶硅层形成电阻器。
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19.发明申请公开(公告)号：US20080120580A1
公开(公告)日：2008-05-22
申请号：US11875193
申请日：2007-10-19
IPC分类号： G06F17/50
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L21/76885
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure comprises an insulating layer of a dielectric material, an opening having sidewalls extending from a top surface of the insulating layer toward a bottom surface of the insulating layer, and a conductive feature disposed in the opening. The design structure includes a top capping layer disposed on at least a top surface of the conductive feature and a conductive liner layer disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer of the design structure has sidewall portions that project above the top surface of the insulating layer adjacent to the sidewalls of the opening.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括介电材料的绝缘层，具有从绝缘层的顶表面朝向绝缘层的底表面延伸的侧壁的开口以及设置在该开口中的导电特征。 该设计结构包括设置在导电特征的至少顶表面上的顶盖层和至少沿开口的侧壁设置在绝缘层和导电特征之间的导电衬垫层。 该设计结构的导电衬里层具有侧壁部分，该侧壁部分突出在邻近开口侧壁的绝缘层顶表面上方。
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20.发明授权Dielectric material with a reduced dielectric constant and methods of manufacturing the same 失效具有降低的介电常数的介电材料及其制造方法公开(公告)号：US07948084B2
公开(公告)日：2011-05-24
申请号：US11928913
申请日：2007-10-30
IPC分类号： H01L23/48
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02238 , H01L21/02252 , H01L21/31633 , H01L21/7682 , H01L21/76831
摘要： In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了制造介电常数降低的介电材料的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成包括沟槽的电介质材料层; 以及（2）通过沿着沟槽的侧壁和底部中的至少一个形成电介质材料层中的多个气隙，从而在电介质材料层中形成包层区域，从而降低电介质材料的有效介电常数 。 提供了许多其他方面。
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