公开(公告)号：US20180061464A1

公开(公告)日：2018-03-01

申请号：US15672310

申请日：2017-08-09

Applicant: Winbond Electronics Corp.

Inventor： Kazuki Yamauchi

IPC: G11C7/12 ,  G11C11/413 ,  G11C7/14 ,  G11C7/18

CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C7/14 ,  G11C7/18 ,  G11C11/413 ,  G11C16/0483 ,  G11C16/24 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2207/005

Abstract: The invention provides a semiconductor memory device and a reading method thereof, which are capable of suppressing a peak current when pre-charging a bit line are provided. The reading method of a flash memory of the present invention includes steps of: pre-charging a selected bit line; and reading a voltage or a current of the pre-charged selected bit line. The step of pre-charging is performed by pre-charging a sense node SNS to Vcc−Vth at a time t1, pre-charging a node TOBL to VCLAMP2 at a time t2, pre-charging the node TOBL to VCLAMP1 at a time t5, and pre-charging the sense node SNS to Vcc at a time t6.

公开(公告)号：US09218888B2

公开(公告)日：2015-12-22

申请号：US14039341

申请日：2013-09-27

Applicant: Winbond Electronics Corp.

Inventor： Kazuki Yamauchi ,  Katsutoshi Suito ,  Oron Michael ,  Jongjun Kim ,  Youn-Cherl Shin

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C7/06

CPC classification number: G11C16/26 ,  G11C7/06 ,  G11C16/0483 ,  G11C16/10

Abstract: A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output.

Abstract translation: 非挥发性半导体存储器包括存储器阵列，根据地址选择页面的选择设备，数据存储设备，存储页面数据以及输出存储的数据的输出设备。 数据存储装置包括从存储器阵列的选定页面接收数据的第一数据存储装置，从第一数据存储装置接收数据的第二数据存储装置，以及配置在第一和第二数据存储装置之间的数据发送装置 。 当第二数据存储装置的第一部分中的数据被输出时，数据传输装置将第一数据存储装置的第二部分的数据发送到第二数据存储装置，并且在第一数据存储装置的第一部分中发送数据 在第二数据存储装置的第二部分中的数据被输出时，发送到第二数据存储装置。

公开(公告)号：US11068202B2

公开(公告)日：2021-07-20

申请号：US16198782

申请日：2018-11-22

Applicant: Winbond Electronics Corp.

Inventor： Kazuki Yamauchi

IPC: G06F3/06

Abstract: The disclosure prevents inconsistencies in a busy state between a master side memory chip and a slave side memory chip during a reset operation. A flash memory device (100) of the disclosure includes a master side memory chip (200) and at least one slave side memory chip (300). A controller (230) of the master side memory chip (200) selects the master side memory chip or the slave side memory chip based on an externally inputted address, and performs a reset of the selected memory chip when a reset command is inputted. The data read from a specific area of a memory cell array of the master side memory chip is set in a register. The controller (230) controls a readout of the reset in a manner that time required for setting the data of the register is longer than time required for the reset of the selected memory chip.

公开(公告)号：US10665304B2

公开(公告)日：2020-05-26

申请号：US16209115

申请日：2018-12-04

Applicant: Winbond Electronics Corp.

Inventor： Makoto Senoo ,  Hiroki Murakami ,  Kazuki Yamauchi

IPC: G11C7/10 ,  G11C16/32 ,  G11C16/04 ,  G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C7/22 ,  G11C16/26 ,  G11C7/20

Abstract: A semiconductor memory device which is able to perform a power sequence with high reliability is provided. When a power from an external device is supplied, the controller of the flash memory of the invention is configured to read codes stored in a read-only memory in synchronization with a clock signal to perform a power-on sequence. In addition, the controller is further configured to deactivate the clock signal so as to pause the power-on sequence when it has been detected during the power-on sequence that the voltage of the power is not greater than a threshold, and to activate the clock signal to resume the power-on sequence when it is detected that the voltage of the supplied power exceeds the threshold again.

公开(公告)号：US10395753B2

公开(公告)日：2019-08-27

申请号：US14470948

申请日：2014-08-28

Applicant: Winbond Electronics Corp.

Inventor： Kazuki Yamauchi

IPC: G11C29/52 ,  G11C16/34 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F3/06 ,  G11C16/10 ,  G06F11/00 ,  G11C11/56 ,  G11C29/04

Abstract: A semiconductor memory device is provided to keep data reliability while decreasing programming time. A NAND flash memory loads programming data from an external input/output terminal to a page buffer/sense circuit. A detecting circuit for monitoring the programming data detects whether the programming data is a specific bit string. If it is detected that the programming data is not a specific bit string, a transferring/writing circuit transfers the programming data kept by the page buffer/sense circuit to an error checking correction (ECC) circuit, and an ECC code generated by an ECC operation is written to the page buffer/sense circuit. If it is detected that the programming data is a specific bit string, transfer of the programming data kept by the page buffer/sense circuit is forbidden and a known ECC code corresponding to the specific bit string is written to the page buffer/sense circuit.

公开(公告)号：US20190163401A1

公开(公告)日：2019-05-30

申请号：US16198782

申请日：2018-11-22

Applicant: Winbond Electronics Corp.

Inventor： Kazuki Yamauchi

IPC: G06F3/06

Abstract: The disclosure prevents inconsistencies in a busy state between a master side memory chip and a slave side memory chip during a reset operation. A flash memory device (100) of the disclosure includes a master side memory chip (200) and at least one slave side memory chip (300). A controller (230) of the master side memory chip (200) selects the master side memory chip or the slave side memory chip based on an externally inputted address, and performs a reset of the selected memory chip when a reset command is inputted. The data read from a specific area of a memory cell array of the master side memory chip is set in a register. The controller (230) controls a readout of the reset in a manner that time required for setting the data of the register is longer than time required for the reset of the selected memory chip.

公开(公告)号：US20190156899A1

公开(公告)日：2019-05-23

申请号：US16192775

申请日：2018-11-15

Applicant: Winbond Electronics Corp.

Inventor： Kazuki Yamauchi ,  Makoto Senoo ,  Hiroki Murakami

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04

Abstract: A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.

公开(公告)号：US20170229184A1

公开(公告)日：2017-08-10

申请号：US15239763

申请日：2016-08-17

Applicant: Winbond Electronics Corp.

Inventor： Kazuki Yamauchi

IPC: G11C16/14 ,  G11C16/34 ,  G11C29/52 ,  G11C29/44 ,  G06F11/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/14 ,  G06F11/1068 ,  G11C7/20 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409

Abstract: A semiconductor memory device, an erasing method and a programming method thereof which can improve yields and utilization efficiency of a memory array are provided. The semiconductor memory device includes a memory array, which includes a plurality of NAND strings; a page buffer/sensing circuit (170), which is connected to the NAND strings of the memory array through bit lines and outputs whether the NAND strings include failures; and a detecting circuit (200), which is connected to the plurality of page buffer/sensing circuits (170) and detects a number of the failures among the NAND strings of a selected block. The block is determined to be usable when the number of the failures among the NAND strings detected by the detecting circuit (200) is less than or equal to a fixed number, and the block is determined to be unusable as a bad block when the number of the failures exceeds the fixed number.