公开(公告)号：US11336287B1

公开(公告)日：2022-05-17

申请号：US17196574

申请日：2021-03-09

Applicant: Xilinx, Inc.

Inventor： Javier Cabezas Rodriguez ,  Juan J. Noguera Serra ,  David Clarke ,  Sneha Bhalchandra Date ,  Tim Tuan ,  Peter McColgan ,  Jan Langer ,  Baris Ozgul

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17768 ,  H03K19/17758 ,  H03K19/17796

Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.

公开(公告)号：US20190303328A1

公开(公告)日：2019-10-03

申请号：US15944617

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H.K. Balski ,  Juan J. Noguera Serra ,  David Clarke ,  Tim Tuan ,  Peter McColgan ,  Zachary Dickman ,  Baris Ozgul ,  Jan Langer

IPC: G06F13/40 ,  G06F13/16

Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.

公开(公告)号：US12164451B2

公开(公告)日：2024-12-10

申请号：US17663824

申请日：2022-05-17

Applicant: Xilinx, Inc.

Inventor： David Patrick Clarke ,  Peter McColgan ,  Juan J. Noguera Serra ,  Tim Tuan ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Javier Cabezas Rodriguez ,  Pedro Miguel Parola Duarte ,  Zachary Blaise Dickman

IPC: G06F13/28 ,  G06F15/80

Abstract: An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.

公开(公告)号：US11848670B2

公开(公告)日：2023-12-19

申请号：US17659423

申请日：2022-04-15

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC: H03K19/1776 ,  G11C5/02 ,  H03K19/17764 ,  H03K19/17784

CPC classification number: H03K19/1776 ,  G11C5/025 ,  H03K19/17764 ,  H03K19/17784

Abstract: An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.

公开(公告)号：US11323391B1

公开(公告)日：2022-05-03

申请号：US16833029

申请日：2020-03-27

Applicant: XILINX, INC.

Inventor： Peter McColgan ,  David Clarke ,  Goran Hk Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Tim Tuan

IPC: H04L12/935 ,  G06F13/28 ,  H04L49/00

Abstract: Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.

公开(公告)号：US10990552B1

公开(公告)日：2021-04-27

申请号：US15944464

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran Hk Bilski ,  Peter McColgan ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F13/40 ,  G06F13/42

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.