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    High bandwidth chip-to-chip interface using HBM physical interface
    11.
    发明授权
    High bandwidth chip-to-chip interface using HBM physical interface 有权

    公开(公告)号：US10410694B1

    公开(公告)日：2019-09-10

    申请号：US16048084

    申请日：2018-07-27

    Applicant: Xilinx, Inc.

    Inventor： Ygal Arbel ,  Sagheer Ahmad ,  Balakrishna Jayadev

    IPC: G11C7/10 ,  G06F11/10 ,  G06F3/06

    Abstract: Techniques related to a high bandwidth interface (HBI) for communication between multiple host devices on an interposer are described. In an example, the HBI repurposes a portion of the high bandwidth memory (HBM) interface, such as the physical layer. A computing system is provided. The computing system includes a first host device and at least a second host device. The first host device is a first die on an interposer and the second host device is a second die on the interposer. The first host device and the second host device are interconnected via at least one HBI. The HBI implements a layered protocol for communication between the first host device and the second host device. The layered protocol includes a physical layer protocol that is configured according to a HBM physical layer protocol.

    Controlling exclusive access using supplemental transaction identifiers
    12.
    发明授权
    Controlling exclusive access using supplemental transaction identifiers 有权

    公开(公告)号：US10176131B1

    公开(公告)日：2019-01-08

    申请号：US15717650

    申请日：2017-09-27

    Applicant: Xilinx, Inc.

    Inventor： Ygal Arbel

    IPC: G06F13/00 ,  G06F13/364 ,  G06F13/42 ,  G06F13/40

    Abstract: A circuit arrangement that includes master circuits generating access transactions, and each access transaction includes an address, a interconnect master identifier, and a system management master identifier. A slave circuit is coupled to the one or more master circuits and is configured to generate responses to the access transactions. Each response includes an interconnect master identifier from one of the plurality of access transactions. An interconnect circuit routes the access transactions to the slave circuit and routes the responses to the one or more master circuits according to the interconnect master identifiers. Exclusive access control circuitry controls exclusive access to the slave circuit based on the value of the system management master identifiers and addresses in the access transactions.

    Circuits for and methods of enabling the access to data
    14.
    发明授权
    Circuits for and methods of enabling the access to data 有权
    用于访问数据的电路和方法

    公开(公告)号：US09558129B2

    公开(公告)日：2017-01-31

    申请号：US14301008

    申请日：2014-06-10

    Applicant: Xilinx, Inc.

    Inventor： Ygal Arbel ,  James J. Murray ,  Hyun W. Kwon ,  Nishit Patel

    IPC: G06F13/00 ,  G06F12/14 ,  G06F13/30 ,  G06F13/28

    CPC classification number: G06F12/145 ,  G06F13/00 ,  G06F13/28 ,  G06F13/30

    Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

    Abstract translation: 描述了一种能够访问数据的电路。 该电路包括存储具有第一预定大小的数据块的存储器件; 以及直接存储器访问电路，其耦合到所述存储器件，所述直接存储器电路访问具有大于所述第一预定大小的第二预定尺寸的数据有效载荷; 其中所述直接存储器访问电路响应于具有对应于存储在所述存储器件中的预定数量的数据块的多个地址的描述符来访问所述数据有效载荷。 还公开了一种能够访问数据的方法。

    BRIDGING INTER-BUS COMMUNICATIONS
    15.
    发明申请
    BRIDGING INTER-BUS COMMUNICATIONS 有权
    桥接通信通信

    公开(公告)号：US20160004656A1

    公开(公告)日：2016-01-07

    申请号：US14325238

    申请日：2014-07-07

    Applicant: Xilinx, Inc.

    Inventor： Ygal Arbel ,  Sagheer Ahmad ,  Sarosh I. Azad

    IPC: G06F13/364 ,  G06F13/40

    CPC classification number: G06F13/404 ,  G06F12/1441 ,  G06F12/145 ,  G06F21/78 ,  G06F21/85

    Abstract: Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address.

    Abstract translation: 公开了用于桥接第一和第二总线之间的通信的方法。 地址转换信息和相关的安全指示符存储在存储器中。 来自第一总线的每个访问请求包括第一请求者安全指示符和所请求的地址。 基于请求者安全指示符和与所请求地址的地址转换信息相关联的安全指示符，来自第一总线并被引导到第二总线的每个访问请求被拒绝或翻译并传送到第二总线。 从第二总线到第一总线的每个访问请求包括所请求的地址，并且访问请求被转换并且与与所请求地址的地址转换信息相关联的安全指示符一起被传送到第一总线。

    NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES
    17.
    发明公开
    NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES 审中-公开

    公开(公告)号：US20230370392A1

    公开(公告)日：2023-11-16

    申请号：US17663376

    申请日：2022-05-13

    Applicant: Xilinx, Inc.

    Inventor： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel ,  Aman Gupta

    IPC: H04L49/109

    CPC classification number: H04L49/109

    Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.

    NoC relaxed write order scheme
    18.
    发明授权
    NoC relaxed write order scheme 有权

    公开(公告)号：US11714779B2

    公开(公告)日：2023-08-01

    申请号：US16830142

    申请日：2020-03-25

    Applicant: XILINX, INC.

    Inventor： Abbas Morshed ,  Ygal Arbel ,  Eun Mi Kim

    IPC: G06F15/78 ,  G06F5/10 ,  G06F9/38 ,  G06F13/40

    CPC classification number: G06F15/7825 ,  G06F5/10 ,  G06F9/38 ,  G06F13/4027 ,  G06F2205/064 ,  G06F2213/0038

    Abstract: Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.

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