公开(公告)号：US06998668B2

公开(公告)日：2006-02-14

申请号：US10246654

申请日：2002-09-19

申请人： Yasunobu Nakase ,  Hiromi Notani

发明人： Yasunobu Nakase ,  Hiromi Notani

IPC分类号： H01L29/94

CPC分类号： H01L27/0222 ,  H01L27/0805 ,  H03K3/356008 ,  H03K3/356113 ,  H03K17/063 ,  H03K17/102 ,  H03K17/223 ,  H03K19/00315 ,  H03K19/018521

摘要： A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply.The semiconductor integrated circuit device includes a level shifter 6 and two capacitors N10 and C0. The level shifter 6 receives an input signal and converts the received signal to a signal having a voltage amplitude greater than that of the received signal, then to provide the signal to a node D3. The capacitor N10 is connected to the node D3, and the capacitor C0 is connected in series with the capacitor N10. The capacitor N10 is formed of a MOS transistor having a gate connected to the node D3 and a source and a drain both connected to the capacitor C0.

摘要翻译： 提供了一种半导体集成电路器件，其中从其发送电平移位器的输出信号的节点可以被初始化，使得其电位在供电时被设置为期望的逻辑电平。

公开(公告)号：US06930941B2

公开(公告)日：2005-08-16

申请号：US10677012

申请日：2003-10-02

申请人： Yasunobu Nakase

发明人： Yasunobu Nakase

IPC分类号： G11C11/417 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C11/419 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/065

摘要： A local sense amplifier drives a global bit line pair by potentials of data storage nodes when a global word line attains an H level. A global sense amplifier amplifies the potential difference of data storage nodes when a global sense enable signal attains an H level. The global sense enable signal is inverted by an inverter to be provided to a global word driver. When the global word line attains an L level by the global word driver, the local sense amplifier suppresses the drive of the global bit line pair.

摘要翻译： 当全局字线达到H电平时，本地读出放大器通过数据存储节点的电位驱动全局位线对。 当全局感测使能信号达到H电平时，全局读出放大器放大数据存储节点的电位差。 全局感测使能信号由反相器反相，以提供给全局字驱动器。 当全局字线由全局字驱动器达到L电平时，局部读出放大器抑制全局位线对的驱动。

公开(公告)号：US6160434A

公开(公告)日：2000-12-12

申请号：US177379

申请日：1998-10-23

申请人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe

发明人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe

IPC分类号： H03K5/00 ,  H03K5/13

CPC分类号： H03K5/133 ,  H03K2005/00039 ,  H03K2005/00286

摘要： Transistors (MP1 and MP2) supply a current (I.sub.0) for nodes (K and L), respectively. Transistors (MN10 and MN11) draw the same current from nodes (K and L), respectively. A parallel connection of serial connections (N1 and N2) draws a current (I.sub.1) from the node (K) only when an exclusive OR of clocks (S1 and S2) is "H". On the other hand, a parallel connection of serial connections (N3 and N4) draws a current (I.sub.1) from the node (L) only when the exclusive OR of clocks (S1 and S2) is "L". When the current (I.sub.1) is drawn from the node (K), the current (I.sub.1) flows out from the node (L) and when the current (I.sub.1) is drawn from the node (L), the current (I.sub.1) flows into the node (L). In the serial connections (N1 to N4), each of the clocks (S1 and S2) and their inverted signals (S1B and S2B) is applied to one of the gates of the transistors (MN1 to MN8) and therefore a uniform input load is obtained. With this configuration provided is a 90-degree phase shifter which achieves the uniform input load to improve a phase offset.

摘要翻译： 晶体管（MP1和MP2）分别为节点（K和L）提供电流（I0）。 晶体管（MN10和MN11）分别从节点（K和L）绘出相同的电流。 串行连接（N1和N2）的并联连接仅在时钟（S1和S2）的异或“为”H“时从节点（K）抽出电流（I1）。 另一方面，仅当时钟（S1和S2）的异或为“L”时，串行连接（N3和N4）的并联连接从节点（L）抽出电流（I1）。 当从节点（K）抽出电流（I1）时，电流（I1）从节点（L）流出，当电流（I1）从节点（L）抽出时，电流（I1）流 进入节点（L）。 在串行连接（N1〜N4）中，每个时钟（S1和S2）及其反相信号（S1B和S2B）被施加到晶体管（MN1至MN8）的一个栅极，因此均匀的输入负载 获得。 所提供的这种配置是实现均匀输入负载以提高相位偏移的90度移相器。

公开(公告)号：US6101151A

公开(公告)日：2000-08-08

申请号：US196245

申请日：1998-11-20

申请人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

发明人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1072

摘要： In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to "L" level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.

摘要翻译： 在同步半导体存储器件中，来自内部定时时钟信号产生电路的内部时钟信号以树形式被驱动电路分支并且被施加到输出缓冲器和数据与内部时钟信号同步输出， 第一级的电路由NAND门和反相器构成。 当暂时停止输出时，使能信号被设置为“L”电平，使得与非门关闭，从而停止对每个驱动电路的时钟信号的输出，从而降低功耗。

公开(公告)号：US5963502A

公开(公告)日：1999-10-05

申请号：US112439

申请日：1998-07-09

申请人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

发明人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  H03L7/06 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.

摘要翻译： 作为包括在PLL电路中的压控振荡器，具有与循环不同的结构的电压控制延迟电路，该PLL电路又由外部时钟信号产生内部时钟信号，由PLL电路的控制电压控制， 电压控制延迟电路的延迟输出由选择电路根据游标调节计数器的输出信号选择，以产生读时钟信号。 因此，可以实现用于优化控制器中的数据输入定时的游标，其总是具有恒定的延迟量，而与操作环境的变化无关。

公开(公告)号：US5621693A

公开(公告)日：1997-04-15

申请号：US632147

申请日：1996-04-15

申请人： Yasunobu Nakase

发明人： Yasunobu Nakase

IPC分类号： G11C11/413 ,  G11C11/412 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C11/419 ,  G11C11/412

摘要： A power source potential VDD and a ground potential GND are supplied to a memory cell which belongs to a selected column. The power source potential VDD and an intermediate potential V.sub.p are supplied to a memory cell which belongs to a non-selected column. Even if an access transistor of the memory cell which belongs to a selected word line and the non-selected column conducts, a current which flows in a drive transistor is suppressed.

摘要翻译： 电源电位VDD和地电位GND被提供给属于所选列的存储单元。 电源电位VDD和中间电位Vp被提供给属于未选列的存储单元。 即使属于所选字线的存储单元的存取晶体管和未选择的列导通，也抑制了在驱动晶体管中流动的电流。

公开(公告)号：US5574687A

公开(公告)日：1996-11-12

申请号：US533550

申请日：1995-09-25

申请人： Yasunobu Nakase

发明人： Yasunobu Nakase

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/419

摘要： There is disclosed a rapidly and correctly readable semiconductor device wherein a clamping transistor (Pcr.sub.-- 0) having a threshold voltage (Vthp) precharges a pair of bit lines (BIT.sub.-- 0, BIT.sub.-- 1) at a precharge potential (VDD-.vertline.Vthp.vertline.) when transistors (Pprc.sub.-- 0, Pprc.sub.-- 1) are conducting, and a write circuit (3) includes a clamping transistor (Pcr.sub.-- 1) having the same threshold voltage (Vthp) as the clamping transistor (Pcr.sub.-- 0), and inverters (23, 24) responsive to input data (DIN.sub.-- 0, DIN.sub.-- 1) for outputting signals which are "H" at the precharge potential (VDD-.vertline.Vthp.vertline.) and "L" at the ground potential to a pair of write input lines (WD.sub.-- 0, WD.sub.-- 1), respectively.

摘要翻译： 公开了一种快速且正确读取的半导体器件，其中具有阈值电压（Vthp）的钳位晶体管（Pcr-0）预充电一个预充电电位（VDD-| Vthp）的位线（BIT-0，BIT-1） （Pprc-0，Pprc-1）导通，并且写入电路（3）包括具有与钳位晶体管（Pcr-0）相同的阈值电压（Vthp）的钳位晶体管（Pcr-1） 以及响应于输入数据（DIN-0，DIN-1）的反相器（23,24），用于输出在预充电电位（VDD- | Vthp |）处为“H”的信号，并将在地电位处输出“L” 的写入输入线（WD-0，WD-1）。

公开(公告)号：US06392897B1

公开(公告)日：2002-05-21

申请号：US09131688

申请日：1998-08-10

申请人： Yasunobu Nakase ,  Tsutomu Yoshimura ,  Yoshikazu Morooka ,  Naoya Watanabe

发明人： Yasunobu Nakase ,  Tsutomu Yoshimura ,  Yoshikazu Morooka ,  Naoya Watanabe

IPC分类号： H01R1216

CPC分类号： H05K1/14 ,  H05K1/117 ,  H05K3/403 ,  H05K2201/09481 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K2203/1572

摘要： A circuit module includes a connector terminal (4A) provided on a front surface of a printed wiring board (2) and connected to a data pin (DQt) of a memory IC (3) through an interconnect line (5a). A conductive connector terminal (4c) corresponds to the connector terminal (4a) and is provided on a back surface of the printed wiring board (2). A through hole (16) extends between part of the front surface of the printed wiring board (2) where the connector terminal (4a) is formed and part of the back surface thereof where the conductive connector terminal (4c) is formed. A conductor fills the through hole (16), thereby suppressing skews resulting from a difference in interconnect line length on the circuit module and decreasing a stub capacitance to achieve the reduction in power consumption.

摘要翻译： 电路模块包括设置在印刷电路板（2）的前表面并通过互连线（5a）连接到存储器IC（3）的数据引脚（DQt）的连接器端子（4A）。 导电连接器端子（4c）对应于连接器端子（4a）并且设置在印刷电路板（2）的背面上。 在形成有连接器端子（4a）的印刷电路板（2）的前表面的一部分和形成导电连接器端子（4c）的背面的一部分之间延伸有一个通孔（16）。 导体填充通孔（16），从而抑制由电路模块上的互连线长度的差异引起的偏移，并且减小短截线电容以实现功耗的降低。

公开(公告)号：US6128208A

公开(公告)日：2000-10-03

申请号：US401185

申请日：1999-09-23

申请人： Niichi Itoh ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Chikayoshi Morishima

发明人： Niichi Itoh ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Chikayoshi Morishima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/02

CPC分类号： H01L27/10844 ,  H01L27/10897

摘要： Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.

摘要翻译： 提供一种具有布局结构的半导体存储器，其中存储单元具有优异的图案化可控性。 存储单元阵列区域1的一个存储单元单元的存储单元的元件部件（有源区域10至15和21至23以及多晶硅区域31至42）的图案与外围虚拟元件的虚设单元相同 单元区域3，并且两个图案相对于边界线BC1呈现线对称关系。 此外，存储单元阵列区域1的一个存储单元单元的存储单元的图案与电力布线区域2的虚设单元的图案相同，并且两个图案相对于边界线呈现线对称关系 BC2。

公开(公告)号：US5994934A

公开(公告)日：1999-11-30

申请号：US111875

申请日：1998-07-08

申请人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe ,  Harufusa Kondoh ,  Hiromi Notani

发明人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe ,  Harufusa Kondoh ,  Hiromi Notani

IPC分类号： G06F1/10 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/095 ,  H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/095

摘要： Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.

摘要翻译： 提供了可以在不增加延迟线的可变延迟时间范围的情况下执行精确的延迟同步操作的DLL电路。 DLL电路包括相位比较器（3），电荷泵（6），LPF（8）和延迟线（9），并且操作以匹配输入信号（CLKIN）和反馈信号（FBCLK）的相位， 。 相位比较器（3）总是输出在复位操作之后的初始操作时延迟线（9）的延迟时间增加的相位比较结果。 在执行复位时，LPF（8）输出指示由于延迟线（9）引起的延迟时间变为最小的延迟调整信号（S8）。