公开(公告)号：US07199022B2

公开(公告)日：2007-04-03

申请号：US10814627

申请日：2004-04-01

申请人： Kan Yasui ,  Toshiyuki Mine ,  Yasushi Goto ,  Natsuki Yokoyama

发明人： Kan Yasui ,  Toshiyuki Mine ,  Yasushi Goto ,  Natsuki Yokoyama

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  Y10S438/907

摘要： In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.

摘要翻译： 为了实现根据本发明的隔离沟槽形成方法，其中可以容易地控制氮化硅膜衬垫的结构并且允许器件特征长度的减小和在隔离沟槽中发生的应力的减小， 氮化硅膜衬垫首先沉积在形成在硅衬底上的沟槽的内壁上。 用于填充沟槽内部的第一嵌入式绝缘体膜的上表面向下凹入以暴露氮化硅膜衬垫的上端部分。 接下来，将氮化硅膜衬垫的露出部分转换成诸如氧化硅膜的非氮化硅型绝缘膜。 然后将第二嵌入式绝缘膜沉积在第一嵌入式绝缘膜的上部上，然后将沉积的表面平坦化。

公开(公告)号：US07193281B2

公开(公告)日：2007-03-20

申请号：US11296289

申请日：2005-12-08

申请人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

发明人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

IPC分类号： H01L29/76

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

摘要翻译： 提供如下配置的半导体器件。 在半导体衬底上形成作为绝缘膜的介电常数高于二氧化硅膜的氧化钛膜作为栅极绝缘膜，并且在其上设置栅电极，得到场效应晶体管。 氧化钛膜的栅极长度方向的端部位于栅电极的源极侧和漏极侧的各端部的内侧，氧化钛膜的端部位于 其中栅电极以平面构型与源区和漏区重叠。 该半导体器件以高速度工作，并且具有优异的短沟道特性和驱动电流。 此外，在半导体器件中，导入硅衬底的金属元素的量小。

公开(公告)号：US06833296B2

公开(公告)日：2004-12-21

申请号：US10776215

申请日：2004-02-12

申请人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

发明人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

摘要翻译： 提供如下配置的半导体器件。 在半导体衬底上形成作为绝缘膜的介电常数高于二氧化硅膜的氧化钛膜作为栅极绝缘膜，并且在其上设置栅电极，得到场效应晶体管。 氧化钛膜的栅极长度方向的端部位于栅电极的源极侧和漏极侧的各端部的内侧，氧化钛膜的端部位于 其中栅电极以平面构型与源区和漏区重叠。 该半导体器件以高速度工作，并且具有优异的短沟道特性和驱动电流。 此外，在半导体器件中，导入硅衬底的金属元素的量小。

公开(公告)号：US20060081949A1

公开(公告)日：2006-04-20

申请号：US11296289

申请日：2005-12-08

申请人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

发明人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

IPC分类号： H01L29/94

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

公开(公告)号：US20050104621A1

公开(公告)日：2005-05-19

申请号：US10933272

申请日：2004-09-03

申请人： Takayuki Kawahara ,  Masayuki Miyazaki ,  Yasushi Goto ,  Natsuki Yokoyama ,  Takahiro Onai

发明人： Takayuki Kawahara ,  Masayuki Miyazaki ,  Yasushi Goto ,  Natsuki Yokoyama ,  Takahiro Onai

IPC分类号： H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H03K19/173 ,  H03K19/177

CPC分类号： G11C23/00 ,  H03K19/1776 ,  H03K19/1778

摘要： The present invention relates to an LSI in which functions can be changed, and realizes, particularly, a system LSI in which functions are changed by changing connections of the circuit by use of MEMS switches. A bistable MEMS switch which can maintain states, and exhibits optimal stitching property, i.e., the switch has a very small resistance of several Ω or less in an on-state, and has an infinite resistance in an off-state; is employed. An element in which functions can be changed during operation, is produced by utilizing a wiring layer of a CMOS semiconductor to form the MEMS switch. A semiconductor device exhibiting high-degree of freedom for changing functions, high-speed, and having small area, is realized.

摘要翻译： 本发明涉及可以改变功能的LSI，特别是实现通过使用MEMS开关改变电路的连接来改变功能的系统LSI。 可以保持状态并且表现出最佳缝合性能的双稳态MEMS开关，即开关在导通状态下具有几欧姆或更小的非常小的电阻，并且在断开状态下具有无限电阻; 被雇用。 通过使用CMOS半导体的布线层来形成功能可以在操作期间改变的元件来形成MEMS开关。 实现了具有高自由度，高速度，小面积化的高自由度的半导体装置。

公开(公告)号：US07064400B2

公开(公告)日：2006-06-20

申请号：US11000992

申请日：2004-12-02

申请人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

发明人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

IPC分类号： H01L29/76

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

公开(公告)号：US07772613B2

公开(公告)日：2010-08-10

申请号：US12533740

申请日：2009-07-31

申请人： Haruka Shimizu ,  Natsuki Yokoyama

发明人： Haruka Shimizu ,  Natsuki Yokoyama

IPC分类号： H01L29/80

CPC分类号： H01L29/0619 ,  H01L29/0661 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/8083

摘要： A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side.

摘要翻译： 提供了其中通道电阻降低而不降低其阻断电压的常闭型结型FET。 在使用由碳化硅制成的衬底形成的结型FET中，使沟道区（第二外延层）的杂质浓度高于作为漂移层的第一外延层的杂质浓度。 沟道区域由沟道宽度恒定的第一区域和沟道宽度朝向漏极（衬底）侧变宽的第一区域下方的第二区域形成。 第一外延层和第二外延层之间的边界位于沟道宽度朝向漏极（基板）侧变宽的第二区域中。

公开(公告)号：US20100163935A1

公开(公告)日：2010-07-01

申请号：US12639054

申请日：2009-12-16

申请人： Haruka Shimizu ,  Natsuki Yokoyama

发明人： Haruka Shimizu ,  Natsuki Yokoyama

IPC分类号： H01L29/808

CPC分类号： H01L29/8083 ,  H01L29/42316 ,  H01L29/66068 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/13055 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.

摘要翻译： 在常闭型的结型FET中，提供了能够实现阻断电压的提高和导通电阻的降低的技术。 在使用碳化硅作为衬底材料的接合FET中，杂质被掺杂到栅极区域和沟道形成区域之间的pn结附近，杂质具有与掺杂在栅极中的杂质相反的导电类型 区域和与在沟道形成区域中掺杂的杂质相同。 以这种方式，pn结的杂质分布变得突然，并且形成与沟道形成区域中的栅极区域的pn结的结区域的杂质浓度高于沟道形成区域中的中心区域的杂质浓度， 形成区域和外延层。

公开(公告)号：US07310563B2

公开(公告)日：2007-12-18

申请号：US11320778

申请日：2005-12-30

申请人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

发明人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC分类号： G06F19/00

CPC分类号： C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

摘要： A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.

摘要翻译： 一种用于系统的制造方法，包括通过机构间运送器彼此连接的多个处理装置。 半导体水在处理装置中进行处理，并以不同的时间间隔被传送到规定的处理装置，时间间隔设定为单位时间间隔的N倍。 由于制造系统包括以与单位时间相关的时间间隔周期性地控制的处理装置和装置间运输装置，所以与单位时间相关的间隔，可以有效地进行多个作业的调度以增强优化水平 ，从而提高生产率。

公开(公告)号：US07115943B2

公开(公告)日：2006-10-03

申请号：US11013406

申请日：2004-12-17

申请人： Toshiyuki Mine ,  Natsuki Yokoyama ,  Kan Yasui

发明人： Toshiyuki Mine ,  Natsuki Yokoyama ,  Kan Yasui

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/792

摘要： A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.

摘要翻译： 分离栅结构的MONOS非易失性存储器，其中由热电子和热孔分别执行写入和擦除容易导致电子不被擦除并且保留在选择栅极电极侧壁上的氮化硅膜中，并且结果 在改写耐久性的恶化。 当长时间擦除作为解决该问题的措施时，会出现缺点，例如由擦除电流的增加引起的电路面积的增加和保留特性的劣化。 在本发明中，通过能够进行取向沉积的反应等离子体溅射沉积方法形成氮化硅膜，并且在形成顶部Si氧化物膜时，在选择栅电极侧壁上除去Si氮化物膜。