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    METHOD AND APPARATUS FOR SUPPLYING POWER TO A SEMICONDUCTOR DEVICE USING A CAPACITOR DC SHUNT
    13.
    发明申请
    METHOD AND APPARATUS FOR SUPPLYING POWER TO A SEMICONDUCTOR DEVICE USING A CAPACITOR DC SHUNT 失效
    使用电容器DC SHUNT向半导体器件供电的方法和装置

    公开(公告)号：US20080079136A1

    公开(公告)日：2008-04-03

    申请号：US11943468

    申请日：2007-11-20

    申请人： Yuan-Liang Li

    发明人： Yuan-Liang Li

    IPC分类号： H01L23/48 ,  H01L21/60

    CPC分类号： H05K1/0231 ,  H01L2224/16225 ,  H05K1/0206 ,  H05K1/0212 ,  H05K1/145 ,  H05K3/3494 ,  H05K2201/09481 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/10734

    摘要： A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.

    摘要翻译： 一种用于半导体器件的功率分流器，该半导体器件具有电耦合到母板的主板和集成电路封装，并且具有位于母板和封装之间的间隔部分的类型。 功率分流器包括在母板和半导体器件的封装之间的间隔部分内的电容器。 电容器包括第一类型的导电层，第二类型的导电层和将第一类型导电层与第二类型导电层电隔离的电介质层，其中所述第一导电层和第二导电层形成 主板和封装之间的导电桥。 电容器的布置实现了提供去耦电容的双重功能，其具有在母板和封装之间向芯片负载16提供额外的电流路径的能力。

    Electronic packages having multiple-zone interconnects and methods of manufacture
    20.
    发明授权
    Electronic packages having multiple-zone interconnects and methods of manufacture 有权
    具有多区域互连的电子封装和制造方法

    公开(公告)号：US06717066B2

    公开(公告)日：2004-04-06

    申请号：US10004002

    申请日：2001-11-30

    申请人： Gilroy J. Vandentop ,  Yuan-Liang Li

    发明人： Gilroy J. Vandentop ,  Yuan-Liang Li

    IPC分类号： H01L2348

    CPC分类号： H01L24/73 ,  H01L23/49827 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10659 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49169 ,  H01L2924/00

    摘要： To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system are also described.

    摘要翻译： 为了适应由封装的或未封装的裸片和衬底的不同热膨胀系数（CTE）产生的热应力，封装包含两个或多个不同的互连区域。 位于模具的中心区域中的第一互连区域采用相对较硬的互连结构。 位于模具周边附近的第二互连区采用相对顺应的互连结构。 位于第一和第二互连区之间并具有与第一和第二区之间的顺应性质量的互连结构的附加互连区可以任选地被采用。 在一个实施例中，在第一互连区域中使用提供低电阻的焊接连接，并且在第二互连区域中使用诸如纳米脉冲的顺应连接。 还描述了制造方法以及将包装应用于电子组件，电子系统和数据处理系统。