公开(公告)号：US12302611B2

公开(公告)日：2025-05-13

申请号：US18521584

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lai ,  Yen-Ming Chen ,  Tsung-Lin Lee

IPC: H10D30/69 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H10D62/10 ,  H10D64/66 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US12302595B2

公开(公告)日：2025-05-13

申请号：US17648037

申请日：2022-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bor Chiuan Hsieh ,  Tsai-Jung Ho ,  Po-Cheng Shih ,  Tze-Liang Lee

IPC: H10D30/01 ,  H10D30/62 ,  H10D64/01

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming gate spacers on opposing sides of the dummy gate stack, forming a source/drain region on a side of the dummy gate stack, forming an inter-layer dielectric over the source/drain region, replacing the dummy gate stack with a replacement gate stack, recessing the replacement gate stack to form a recess between the gate spacers, depositing a liner extending into the recess, depositing a masking layer over the liner and extending into the recess, forming an etching mask covering a portion of the masking layer, and etching the inter-layer dielectric to form a source/drain contact opening. The source/drain region is underlying and exposed to the source/drain contact opening. A source/drain contact plug is formed in the source/drain contact opening. A gate contact plug extends between the gate spacers and electrically connecting to the replacement gate stack.

公开(公告)号：US12302553B2

公开(公告)日：2025-05-13

申请号：US17668770

申请日：2022-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Bo-Feng Young ,  Hung Wei Li ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10B12/00 ,  H01L29/10

Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

公开(公告)号：US12300754B2

公开(公告)日：2025-05-13

申请号：US18190754

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Zhiqiang Wu

IPC: H01L29/786 ,  H01L29/423

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

公开(公告)号：US12300739B2

公开(公告)日：2025-05-13

申请号：US18586735

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min Cao ,  Pei-Yu Wang ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

公开(公告)号：US12300717B2

公开(公告)日：2025-05-13

申请号：US17670740

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/786

Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

公开(公告)号：US12300580B2

公开(公告)日：2025-05-13

申请号：US18732879

申请日：2024-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Lun Liu ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chen-En Yen ,  Cheng-Lung Yang ,  Kuanchih Huang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/60

Abstract: Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the plurality of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

公开(公告)号：US12300549B2

公开(公告)日：2025-05-13

申请号：US18309416

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/324 ,  H01L21/768 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US12300539B2

公开(公告)日：2025-05-13

申请号：US18361770

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Yu-Ming Huang ,  Ethan Tseng ,  Ken-Yu Chang ,  Yi-Ying Liu

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H10D30/01 ,  H10D30/62 ,  H10D62/13 ,  H10D62/40 ,  H10D62/832 ,  H10D64/62

Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.

公开(公告)号：US12298664B2

公开(公告)日：2025-05-13

申请号：US18429281

申请日：2024-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Jung Chang ,  Jen-Yang Chung ,  Han-Lung Chang

IPC: G03F7/00 ,  G03F1/66 ,  G03F1/84

Abstract: A method and a system for inspecting an extreme ultra violet mask and a mask pod for such masks is provided. An EUV mask inspection tool inspects a mask retrieved from a mask pod placed on the load port positioned exterior of the mask inspection tool. The inspection process is performed during a selected period of time. After the inspection process is initiated, a robotic handling mechanism such as a robotic arm or an AMHS picks up the mask pod and inspects the mask pod for foreign particles. A mask pod inspection tool determines whether the mask pod needs cleaning or replacing based on a selected swap criteria. The mask pod is retrieved from the mask pod inspection tool and placed on the load port before the selected period of time lapses. This method and system promotes a reduction in the overall time required for inspecting the mask and the mask pod.