公开(公告)号：US08796744B1

公开(公告)日：2014-08-05

申请号：US13812504

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/775

CPC classification number: H01L29/775 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/7786

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极 沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成， 并且沟道层由GeSn合金形成。 根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而 适应高速高频应用。

公开(公告)号：US08765540B2

公开(公告)日：2014-07-01

申请号：US13697072

申请日：2012-05-16

Applicant: Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L27/092 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/76272 ,  H01L21/76283 ,  H01L21/76289 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/66477 ,  H01L29/78

Abstract: The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region, and the doping concentration of the semiconductor auxiliary base layer is higher than that of the semiconductor base. Correspondingly, the present invention also provides a method for manufacturing a semiconductor structure. According to the present invention, the short channel effect can be suppressed, and the device performance can be improved, thereby reducing the cost and simplifying the process.

Abstract translation: 本发明提供了一种半导体结构，其包括：基板，半导体基底，半导体辅助基底层，空腔，栅极堆叠，侧壁间隔物和源极/漏极区域，其中栅极堆叠位于 半导体基地 侧壁间隔件位于栅极叠层的侧壁上; 源极/漏极区域嵌入在半导体基底中并且位于栅极叠层的两侧; 空腔嵌入基板中; 半导体基底悬挂在空腔上方，半导体基底的中间部分的厚度大于半导体基底的两个端部在栅极长度方向上的厚度，而两个端部的厚度 半导体基底沿栅极的宽度方向连接到基板; 并且半导体辅助基极层位于半导体基底的侧壁上并且具有与源极/漏极区相反的掺杂型，并且半导体辅助基极层的掺杂浓度高于半导体基底的掺杂浓度。 相应地，本发明还提供一种制造半导体结构的方法。 根据本发明，可以抑制短通道效应，并且可以提高装置性能，从而降低成本并简化处理。

公开(公告)号：US08669160B2

公开(公告)日：2014-03-11

申请号：US13696308

申请日：2012-05-16

Applicant: Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu ,  Da Yang

Inventor： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu ,  Da Yang

IPC: H01L21/336 ,  H01L21/425

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises providing a semiconductor substrate; forming a dummy gate structure and a spacer surrounding the dummy gate structure on the semiconductor substrate; forming source/drain regions on both sides of the gate structure within the semiconductor substrate using the dummy gate structure and the spacer as a mask; forming an interlayer dielectric layer on the upper surface of the semiconductor substrate, the upper surface of the interlayer dielectric layer being flush with the upper surface of the dummy gate structure; removing at least a part of the dummy gate structure so as to form a trench surrounded by the spacer; performing tilt angle ion implantation into the semiconductor substrate using the interlayer dielectric layer and spacer as a mask so as to form an asymmetric Halo implantation region; sequentially forming a gate dielectric layer and a metal gate in the trench.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括提供半导体衬底; 在所述半导体衬底上形成虚拟栅极结构和围绕所述虚设栅极结构的间隔物; 使用所述虚拟栅极结构和所述间隔物作为掩模，在所述半导体衬底内的所述栅极结构的两侧上形成源极/漏极区域; 在所述半导体衬底的上表面上形成层间电介质层，所述层间电介质层的上表面与所述虚拟栅极结构的上表面齐平; 去除所述伪栅极结构的至少一部分，以形成由所述间隔物包围的沟槽; 使用层间电介质层和间隔物作为掩模对半导体衬底进行倾斜角度离子注入，以形成不对称的光晕注入区域; 在沟槽中依次形成栅介电层和金属栅极。

公开(公告)号：US08647987B2

公开(公告)日：2014-02-11

申请号：US13698283

申请日：2012-06-12

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC classification number: H01L21/30625 ,  H01L21/31053 ,  H01L21/31056 ,  H01L22/26 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.

Abstract translation: 本发明提供了一种改善化学机械平面化工艺的均匀性的方法，包括以下步骤：在基底上形成特征; 在所述特征之间形成第一绝缘隔离层; 平面化第一介电隔离层直到特征被暴露，使得特征之间的第一介电隔离层具有凹陷深度; 在特征和第一介电隔离层上形成第二绝缘隔离层，从而减小特征之间的第二介电隔离层与特征顶部的第二介电隔离层之间的高度差; 平坦化第二介电隔离层，直到特征被暴露。 根据本发明的化学机械平面化工艺的均匀性提高方法，在研磨特征顶部的介电隔离层之后再次形成介电隔离层，使得介电层之间的高度差 并且功能顶部的电介质层被有效地减少，并且特征的凹部得到补偿，从而有效地提高了模内均匀性。

公开(公告)号：US08642471B2

公开(公告)日：2014-02-04

申请号：US13379658

申请日：2011-02-27

Applicant: Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L29/94

CPC classification number: H01L21/28518 ,  H01L21/28185 ,  H01L21/76814 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method for manufacturing a semiconductor structure. The method can effectively reduce the contact resistance between source/drain regions and a contact layer by forming two contact layers of different thickness on the surfaces of the source/drain regions. Further, the present invention provides a semiconductor structure, which has reduced the contact resistance.

Abstract translation: 本发明提供一种半导体结构的制造方法。 该方法可以通过在源极/漏极区域的表面上形成不同厚度的两个接触层来有效地降低源极/漏极区域和接触层之间的接触电阻。 此外，本发明提供一种降低了接触电阻的半导体结构。

公开(公告)号：US08530302B2

公开(公告)日：2013-09-10

申请号：US13576658

申请日：2011-11-22

Applicant: Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

Inventor： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

IPC: H01L21/8238 ,  H01L21/4763

CPC classification number: H01L21/8238 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate. The first hard mask and the second hard mask are removed by etching; a polysilicon layer and a third hard mask are deposited and patterned by lithography and etching to form a gate stack; a dielectric layer is deposited and etched to form first spacers. Source/drain regions and their extensions are then formed by a conventional process, and silicides are formed by silicidation to provide contact and metallization.

Abstract translation: 制造CMOS FET的方法包括在形成常规介电隔离之后在半导体衬底上形成第一界面SiO 2层; 形成堆叠第一高K栅极电介质/第一金属栅极; 沉积第一个硬掩模; 通过光刻和蚀刻图案化第一硬掩模; 蚀刻未被第一硬掩模覆盖的第一金属栅极和第一高K栅极电介质的部分。 然后形成第二界面SiO 2层和第二高K栅极电介质/第二金属栅极的叠层; 通过光刻和蚀刻沉积和图案化第二个硬掩模; 蚀刻未被第二硬掩模覆盖的第二金属栅极和第二高K栅极电介质的部分以露出第一金属栅极上的第一硬掩模。 通过蚀刻去除第一硬掩模和第二硬掩模; 通过光刻和蚀刻沉积多晶硅层和第三硬掩模并图案化以形成栅叠层; 沉积和蚀刻电介质层以形成第一间隔物。 然后通过常规工艺形成源极/漏极区及其延伸，并且通过硅化物形成硅化物以提供接触和金属化。

公开(公告)号：US08906753B2

公开(公告)日：2014-12-09

申请号：US13380857

申请日：2011-08-25

Applicant: Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L29/41733 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7839

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, forming a gate structure on the SOI substrate; etching an SOI layer of the SOI substrate and a BOX layer of the SOI substrate on both sides of the gate structure to form trenches, the trenches exposing the BOX layer and extending partly into the BOX layer; forming sidewall spacers on sidewalls of the trenches; forming inside the trenches a metal layer covering the sidewall spacers, wherein the metal layer is in contact with the SOI layer which is under the gate structure. Accordingly, the present invention further provides a semiconductor structure formed according to aforesaid method. The manufacturing method and the semiconductor structure according to the present invention make it possible to reduce capacitance between a metal layer and a body silicon layer of an SOI substrate when a semiconductor device is in operation, which is therefore favorable for enhancing performance of the semiconductor device.

公开(公告)号：US08829642B2

公开(公告)日：2014-09-09

申请号：US13512330

申请日：2012-04-09

Applicant: Haizhou Yin ,  Wei Jiang

Inventor： Haizhou Yin ,  Wei Jiang

IPC: H01L21/76 ,  H01L29/02

CPC classification number: H01L21/76232 ,  H01L29/7833

Abstract: The present invention discloses a semiconductor device, which comprises: a substrate, and a shallow trench isolation in the substrate, characterized in that, the semiconductor device further comprises a stress release layer between the substrate and the shallow trench isolation. In the semiconductor device and the method for manufacturing the same according to the present invention, the stresses accumulated during the formation of the STI can be released by interposing the stress release layer made of a softer material between the substrate and the STI, thereby reducing the leakage current of the substrate of the device and improving the device reliability.

Abstract translation: 本发明公开了一种半导体器件，其包括：衬底和衬底中的浅沟槽隔离，其特征在于，所述半导体器件还包括在所述衬底和所述浅沟槽隔离之间的应力释放层。 在根据本发明的半导体器件及其制造方法中，通过在衬底和STI之间插入由较软材料制成的应力释放层，可以释放在形成STI期间累积的应力，从而减少 器件基板的漏电流，提高器件的可靠性。

公开(公告)号：US08574977B2

公开(公告)日：2013-11-05

申请号：US13503358

申请日：2011-11-21

Applicant: Qiuxia Xu ,  Yongliang Li

Inventor： Qiuxia Xu ,  Yongliang Li

IPC: H01L21/8238

CPC classification number: H01L21/26586 ,  H01L21/28088 ,  H01L29/4966

Abstract: The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or oxynitride layer on a semiconductor substrate by rapid thermal oxidation or chemical method after conventional LOCOS or STI dielectric isolation is completed; depositing high-K gate dielectric and performing rapid thermal annealing; depositing a composite metal gate; depositing a barrier metal layer; depositing a polysilicon film and a hard mask and then performing photolithography and etching the hard mask; removing photoresist and etching the polysilicon film, the barrier metal layer, the metal gate, the high-K gate dielectric, and the interface oxide layer in sequence to form a gate stack structure of polysilicon film/barrier metal layer/metal gate/high-K gate dielectric; forming spacers, source/drain implantation in a conventional manner and performing rapid thermal annealing, whereby while source/drain dopants are activated, adjusting of metal gate effective work function of the PMOS device is achieved.

Abstract translation: 本公开提供了一种用于制造栅极堆叠结构并调整PMOS器件的栅极功能的方法，包括：在常规LOCOS之后通过快速热氧化或化学方法在半导体衬底上生长超薄界面氧化物层或氧氮化物层 或STI绝缘隔离完成; 沉积高K栅介质并进行快速热退火; 沉积复合金属门; 沉积阻挡金属层; 沉积多晶硅膜和硬掩模，然后进行光刻和蚀刻硬掩模; 去除光致抗蚀剂并依次蚀刻多晶硅膜，阻挡金属层，金属栅极，高K栅极电介质和界面氧化物层，以形成多晶硅膜/阻挡金属层/金属栅极/ K栅电介质; 以常规方式形成间隔物，源极/漏极注入并执行快速热退火，由此在源极/漏极掺杂剂被激活时，实现了PMOS器件的金属栅极有效功函数的调整。

公开(公告)号：US09049061B2

公开(公告)日：2015-06-02

申请号：US13640733

申请日：2012-04-11

Applicant: Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

Inventor： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

IPC: H01L27/092 ,  H01L21/265 ,  H04L21/02

CPC classification number: H04L21/02 ,  H01L21/265 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

Abstract: This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.

Abstract translation: 本发明公开了一种CMOS器件，其包括：第一MOSFET; 与第一MOSFET的类型不同的第二MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力层; 以及覆盖所述第二MOSFET的第二应力层，其中所述第二应力层掺杂有离子，并且因此具有不同于所述第一应力的第二应力。 本发明的CMOS器件及其制造方法利用分离离子注入方法实现双重应力衬垫，而不需要通过光刻/光刻技术去除PMOS区域上的拉伸应力层或NMOS区域上的压应力层， 蚀刻，从而简化了工艺并降低了成本，并且同时防止了NMOS区域或PMOS区域上的衬垫中的应力不受由沉积工艺的热处理引起的损伤。