公开(公告)号：US08502305B2

公开(公告)日：2013-08-06

申请号：US13421816

申请日：2012-03-15

申请人： Tsuyoshi Ohta ,  Tatsuya Nishiwaki ,  Norio Yasuhara ,  Masatoshi Arai ,  Takahiro Kawano

发明人： Tsuyoshi Ohta ,  Tatsuya Nishiwaki ,  Norio Yasuhara ,  Masatoshi Arai ,  Takahiro Kawano

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/2255 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/861

摘要： According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.

摘要翻译： 根据实施例，半导体器件包括第一导电类型的半导体层，设置在半导体层上的第二导电类型的基极区域和设置在基极区域上的第二导电类型的第一接触区域。 该器件包括设置在穿过第一接触区域和基极区域的沟槽中的栅电极，以及设置在栅极上并包含第一导电型杂质元素的层间绝缘膜。 该器件还包括设置在层间绝缘膜和第一接触区域之间的第一导电类型的源极区域，源极区域与层间绝缘膜的侧面接触并且在基极区域中延伸。

公开(公告)号：US20130069147A1

公开(公告)日：2013-03-21

申请号：US13421816

申请日：2012-03-15

申请人： Tsuyoshi OHTA ,  Tatsuya NISHIWAKI ,  Norio YASUHARA ,  Masatoshi ARAI ,  Takahiro KAWANO

发明人： Tsuyoshi OHTA ,  Tatsuya NISHIWAKI ,  Norio YASUHARA ,  Masatoshi ARAI ,  Takahiro KAWANO

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/2255 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/861

摘要： According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.

摘要翻译： 根据实施例，半导体器件包括第一导电类型的半导体层，设置在半导体层上的第二导电类型的基极区域和设置在基极区域上的第二导电类型的第一接触区域。 该器件包括设置在穿过第一接触区域和基极区域的沟槽中的栅电极，以及设置在栅极上并包含第一导电型杂质元素的层间绝缘膜。 该器件还包括设置在层间绝缘膜和第一接触区域之间的第一导电类型的源极区域，源极区域与层间绝缘膜的侧面接触并且在基极区域中延伸。

公开(公告)号：US20120217575A1

公开(公告)日：2012-08-30

申请号：US13238525

申请日：2011-09-21

申请人： Tetsuo Matsuda

发明人： Tetsuo Matsuda

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/66787

摘要： According to one embodiment, a method is disclosed for manufacturing semiconductor device. The method can include preparing a semiconductor layer having a drain layer, and a drift region provided from a surface to an inside of the drain layer, the drift region having a first trench extending from a surface to an inside of the drift region. The method can include implanting impurities into the drift region through an opening of the first trench to form a source region for an exposed face of the drift region exposed on an inside wall of the first trench, and implanting impurities into the drift region through the opening of the first trench to form a base region between the source region and the drift region. The method can include forming gate electrode.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法。 该方法可以包括制备具有漏极层的半导体层和从漏极层的表面到内部提供的漂移区域，漂移区域具有从漂移区域的表面延伸到内部的第一沟槽。 该方法可以包括通过第一沟槽的开口将杂质注入到漂移区域中，以形成暴露在第一沟槽的内壁上的漂移区域的暴露面的源极区域，以及通过开口将杂质注入漂移区域 以形成源极区域和漂移区域之间的基极区域。 该方法可以包括形成栅电极。

公开(公告)号：US08174069B2

公开(公告)日：2012-05-08

申请号：US12186231

申请日：2008-08-05

申请人： Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

发明人： Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

IPC分类号： H01L29/94

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0839 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7394 ,  H01L29/7824

摘要： A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.

摘要翻译： 功率半导体器件具有顶表面和相对的底表面，其下面的一部分是半导体衬底的厚部分。 装置的漂移区域的至少一部分具有没有或仅有半导体衬底的薄的部分位于其下方。 顶表面具有高电压端子和与其连接的低电压端子，以允许跨越漂移区域横向施加电压。 在顶表面上设置至少两个MOS（金属氧化物半导体）栅极。 器件在其顶表面处具有至少一个相对高度掺杂的区域，其在所述第一和第二MOS栅极之间延伸并与之接触。 该器件具有改进的防止寄生晶体管触发或闩锁的保护，而不会导致导通电压降或开关速度受损。

公开(公告)号：US20110159650A1

公开(公告)日：2011-06-30

申请号：US13039636

申请日：2011-03-03

申请人： Naohiro Shiraishi

发明人： Naohiro Shiraishi

IPC分类号： H01L21/336

CPC分类号： H01L29/0856 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

摘要： A DMOS type semiconductor device and a method for manufacturing the same are provided. An isolation oxide layer with an ion implantation opening is formed on a semiconductor. A gate oxide film is formed on the semiconductor within the ion implantation opening. A gate is formed on the isolation oxide layer and the gate oxide film. A body layer diffusively formed in the semiconductor by implanting ions of an impurity element having a first conduction type from the ion implantation opening. A regulation layer which is shallower than the body layer is diffusively formed in the body layer by implanting ions of an impurity element having a second conduction type opposite to the first conduction type from the ion implantation opening. A source layer is diffusively formed in the regulation layer by implanting ions of an impurity element having the second conduction type from the ion implantation opening. The regulation layer is formed so as to horizontally extend beyond a region in which a gate bird's beak occurs from an end of the gate toward underlying layers of the gate.

摘要翻译： 提供了一种DMOS型半导体器件及其制造方法。 在半导体上形成具有离子注入开口的隔离氧化物层。 在离子注入开口内的半导体上形成栅极氧化膜。 在隔离氧化物层和栅极氧化膜上形成栅极。 通过从离子注入开口注入具有第一导电类型的杂质元素的离子，在半导体中扩散地形成体层。 通过从离子注入口注入具有与第一导电类型相反的第二导电类型的杂质元素的离子，在体层中散布比体层浅的调节层。 源极层通过从离子注入开口注入具有第二导电类型的杂质元素的离子而在调节层中扩散形成。 调节层形成为水平地延伸超过栅极鸟嘴从栅极的端部朝向栅极的下层发生的区域。

公开(公告)号：US20100065905A1

公开(公告)日：2010-03-18

申请号：US12212489

申请日：2008-09-17

申请人： James Pan

发明人： James Pan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric.

摘要翻译： 半导体结构包括半导体区域中的第一导电类型的漂移区域。 第二导电类型的阱区域在漂移区域之上。 第一导电类型的源极区位于阱区的上部。 第二导电类型的重体区域在阱区域中延伸。 重体区域的掺杂浓度高于阱区域。 第一扩散阻挡区域至少部分地围绕重体区域。 栅电极通过栅极电介质与半导体区域绝缘​​。

公开(公告)号：US07394135B1

公开(公告)日：2008-07-01

申请号：US10905668

申请日：2005-01-14

申请人： Edward Herbert

发明人： Edward Herbert

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0856 ,  H01L29/41741 ,  H01L29/7803 ,  H01L29/7831 ,  H02M3/33576

摘要： A dual source MOSFET comprises a large number of cells diffused into a substrate. The cells are divided into two regions with separate sources and gates but having a common drain connection, the substrate. It is preferred that the source regions be highly interdigitated so that the current at the silicon to metal interface is sufficiently diffuse so that the source from which it originated is indistinguishable, and in switching from one source to the other causes no significant difference in the current density or distribution at the drain connection, provided that the sum of the source currents is constant. The same construction provides a superior ac switch, though no drain connection is needed.

摘要翻译： 双源MOSFET包括扩散到衬底中的大量单元。 电池被分成具有单独的源极和栅极的两个区域，但是具有共同的漏极连接，衬底。 优选地，源极区域被高度交错，使得硅到金属界面处的电流充分地扩散，使得源起始的源不可区分，并且在从一个源切换到另一个源时，电流没有显着差异 密度或分布在漏极连接处，前提是源电流之和是恒定的。 相同的结构提供了卓越的交流开关，尽管不需要排水连接。

公开(公告)号：US20060118811A1

公开(公告)日：2006-06-08

申请号：US10542192

申请日：2004-02-04

申请人： Shen Zheng ,  David Okada

发明人： Shen Zheng ,  David Okada

IPC分类号： H01L29/74

CPC分类号： H01L29/7816 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/41758 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7813 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor device that is comprised to two or more MOSFETs to form a bi-directional power switch. One embodiment of the bi-directional switch is comprised of (a) a semiconductor substrate having an upper surface and a lower surface; (b) a first region of a first conductivity type in said semiconductor substrate and proximate to said upper surface; (c) a first source region and a second source region of a second conductivity type within said first region; (d) a drain region of a second conductivity type formed within said first region and proximate to said upper surface and between said first and second source regions; (e) a first source overlaying and connecting said first source region; (f) a second source overlaying and connecting said second source region; (g) a first gate above said upper surface and placed between said first source and said second source wherein said first gate overlays a portion of said first source region and said drain region; (h) a second gate above said upper surface and placed between said second source and said first gate wherein said second gate overlays a portion of said second source region and said drain region.

摘要翻译： 一种半导体器件，包括两个或多个MOSFET以形成双向电源开关。 双向开关的一个实施例包括（a）具有上表面和下表面的半导体衬底; （b）在所述半导体衬底中并且靠近所述上表面的第一导电类型的第一区域; （c）在所述第一区域内的第二导电类型的第一源极区域和第二源极区域; （d）第二导电类型的漏极区，形成在所述第一区域内并且靠近所述上表面并且在所述第一和第二源极区之间; （e）覆盖并连接所述第一源区的第一源; （f）覆盖并连接所述第二源区的第二源; （g）位于所述上表面之上并位于所述第一源和所述第二源之间的第一栅极，其中所述第一栅极覆盖所述第一源极区域和所述漏极区域的一部分; （h）在所述上表面上方的第二栅极，并且放置在所述第二源极和所述第一栅极之间，其中所述第二栅极覆盖所述第二源极区域和所述漏极区域的一部分。

公开(公告)号：US20240113099A1

公开(公告)日：2024-04-04

申请号：US18309172

申请日：2023-04-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Lin HSU ,  Yu-Ti SU

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/08

CPC分类号： H01L27/0255 ,  H01L27/0629 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0856 ,  H01L29/0873

摘要： An IC device includes first and second CMOS structures positioned in n-type doped regions of a substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first PMOS body and source contacts, and a third electrical connection from an anode of the of the diode to the first NMOS body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the IC device.

公开(公告)号：US20240088273A1

公开(公告)日：2024-03-14

申请号：US18286152

申请日：2022-05-20

申请人： WUXI CHINA RESOURCES HUAJING MICROELECTRONICS CO., LTD.

发明人： PENGFEI JIA ,  QIANG RUI ,  WEI LI

IPC分类号： H01L29/739 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/7396 ,  H01L29/0856 ,  H01L29/452 ,  H01L29/66333

摘要： A vertical semiconductor structure with an integrated sampling structure and a method for manufacturing the same; the vertical semiconductor structure includes a vertical-semiconductor-structure unit cell, a sampling unit cell, a control electrode, a first electrode, a second electrode, and a sampling electrode. The sampling electrode performs real-time sampling of a voltage difference between the first electrode and the second electrode; a PN junction is formed between a first/second P-type diffusion region and a second N-type base region, which forms a potential barrier blocking electron emission from the sampling electrode. Therefore, a voltage signal of the sampling electrode is input into a protection circuit, which detects whether the vertical-semiconductor-structure unit cell is desaturated when it determines that the unit cell is in the open state. Second, a sampling resistor is connected between the sampling electrode and the first electrode to ensure the stable operation of the sampling unit cell.