Multiple differential write clock signals with different phases

    公开(公告)号:US11901039B2

    公开(公告)日:2024-02-13

    申请号:US17556570

    申请日:2021-12-20

    发明人: Keun Soo Song

    摘要: Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (e.g., of a host device) can provide two differential write clock signals to a memory device over an interconnect. The two differential write clock signals may have a phase offset of approximately ninety degrees. Instead of generating its own phase-delayed write clock signals using a component (e.g., a clock divider circuit) that can enter the metastable state, the memory device can use the multiple differential write clocks signals provided by the memory controller to process memory requests.

    Time-to-digital converter circuitry

    公开(公告)号:US11868094B2

    公开(公告)日:2024-01-09

    申请号:US17910437

    申请日:2020-03-17

    IPC分类号: G04F10/00 H03L7/081 H03L7/183

    摘要: A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal (109) and an input clock signal (110) to a digitally represented output signal (139). The TDC circuitry comprises a plurality of constituent TDC:s (101, 102, 103), a reference signal provider (120), and a digital signal combiner (130). Each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183) and a constituent clock signal (110) to a digitally represented constituent output signal (131, 132, 133). The reference signal provider (120) is configured to provide the respective constituent reference signals (181, 182, 183) to each of the constituent TDC:s (101, 102, 103). In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal (109) with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner (130) is configured to provide the digitally represented output signal (139) based on the digitally represented constituent output signals (131, 132, 133) of the constituent TDC:s. A corresponding method and devices comprising the TDC circuitry are also disclosed.

    Delay Lock Loop Circuits and Methods for Operating Same

    公开(公告)号:US20230253970A1

    公开(公告)日:2023-08-10

    申请号:US18301299

    申请日:2023-04-17

    IPC分类号: H03L7/081 H03L7/095

    摘要: Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

    APPARATUSES AND METHODS FOR INDIRECTLY DETECTING PHASE VARIATIONS

    公开(公告)号:US20190199360A1

    公开(公告)日:2019-06-27

    申请号:US16286829

    申请日:2019-02-27

    发明人: Hiroki Takahashi

    IPC分类号: H03L7/081 H03L7/091

    摘要: Apparatuses and methods for indirect phase variation detection are disclosed herein. An example apparatus may include a clock generator circuit comprising a delay-locked loop (DLL) circuit configured to adjust a phase of a clock signal based on a phase of a feedback clock signal during an initial phase-lock operation. The DLL circuit includes a phase deviation detection circuit configured to detect a variation in a phase of the clock signal based on variations in gate delays of an oscillation circuit, and to initiate a subsequent phase-lock operation in response to detecting variations in the gate delays of the oscillation circuit.

    SINGLE-LOCK DELAY LOCKED LOOP WITH CYCLE COUNTER AND METHOD THEREFOR

    公开(公告)号:US20180351560A1

    公开(公告)日:2018-12-06

    申请号:US16059136

    申请日:2018-08-09

    IPC分类号: H03L7/081 G11C11/16 H03L7/14

    摘要: Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.

    Clock alignment scheme for data macros of DDR PHY

    公开(公告)号:US10014866B2

    公开(公告)日:2018-07-03

    申请号:US15707205

    申请日:2017-09-18

    申请人: Invecas, Inc.

    摘要: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.