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    SHARED MEMORY WITH ENHANCED ERROR CORRECTION
    11.
    发明申请
    SHARED MEMORY WITH ENHANCED ERROR CORRECTION 审中-公开

    公开(公告)号：US20170288705A1

    公开(公告)日：2017-10-05

    申请号：US15091195

    申请日：2016-04-05

    申请人： Alibaba Group Holding Limited

    发明人： Shu LI

    IPC分类号： H03M13/29 ,  G11C29/52 ,  G06F11/10 ,  G06F13/40 ,  G06F13/42

    CPC分类号： H03M13/2927 ,  G06F11/1012 ,  G06F13/4068 ,  G06F13/4282 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2948

    摘要： A memory system that detects and corrects bit errors performs a first decoding procedure regarding a serial unit of the encoded data to produce a decoded serial unit. The memory system further determines the first decoding procedure regarding the serial unit was not successful and performs the first decoding procedure regarding a plurality of additional serial units of the encoded data to produce a plurality of additional decoded serial units. The serial unit and the plurality of additional serial units constitute a predefined grouping of the encoded data. The memory system also performs a second decoding procedure regarding a plurality of derivative units to produce a plurality of decoded derivative units. Each successive bit in each of the plurality of derivative units is correlated to a corresponding sequential position in the decoded serial unit and each of the decoded additional serial units.

    MEMORY CONTROLLER AND DECODING METHOD
    12.
    发明申请
    MEMORY CONTROLLER AND DECODING METHOD 审中-公开

    公开(公告)号：US20170257122A1

    公开(公告)日：2017-09-07

    申请号：US15259690

    申请日：2016-09-08

    申请人： Kabushiki Kaisha Toshiba

    发明人： Osamu TORII ,  Haruka OBATA

    IPC分类号： H03M13/45 ,  H03M13/15 ,  G11C29/52 ,  G06F11/10

    CPC分类号： G06F11/1012 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/3707 ,  H03M13/3738 ,  H03M13/3746 ,  H03M13/3753

    摘要： A memory controller according to an embodiment includes a first decoder which calculates first extrinsic value based on a decoding success rate specified using a first table showing a correspondence between first distance information indicating a square Euclidean distance between a first decode word and a first soft input value and a first decoding success rate indicating a probability of a decoding result that the first decode word is correct, and a second decoder which calculates second extrinsic value based on a decoding success rate specified using the second table showing a correspondence second distance information indicating a square Euclidean distance between a second decode word and a second soft input value and a second decoding success rate indicating a probability of a decoding result that the second decode word is correct.

    DATA DEPENDENCY MITIGATION IN DECODER ARCHITECTURE FOR GENERALIZED PRODUCT CODES FOR FLASH STORAGE
    13.
    发明申请
    DATA DEPENDENCY MITIGATION IN DECODER ARCHITECTURE FOR GENERALIZED PRODUCT CODES FOR FLASH STORAGE 审中-公开

    公开(公告)号：US20170222662A1

    公开(公告)日：2017-08-03

    申请号：US15411773

    申请日：2017-01-20

    申请人： SK Hynix Inc.

    发明人： Naveen Kumar ,  Yi-Min Lin ,  Aman Bhatia

    IPC分类号： H03M13/29 ,  H03M13/39 ,  H03M13/37

    CPC分类号： H03M13/2927 ,  H03M13/152 ,  H03M13/1555 ,  H03M13/2909

    摘要： A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. In coarse decoding, the decoder decodes in parallel two or more codewords, which share a common block of bits, to determine error information. Next, the decoder corrects errors in a first codeword based on the error information. Then, it is determined if the shared common block of data bits is corrected. If the shared common data block is updated, then error correction based on the error information is prohibited in codewords sharing the common block of data bits with the first codeword. In fine decoding, a single codeword is decoded at a time for error correction.

    CONCATENATED AND SLIDING-WINDOW POLAR CODING
    14.
    发明申请
    CONCATENATED AND SLIDING-WINDOW POLAR CODING 审中-公开

    公开(公告)号：US20170214416A1

    公开(公告)日：2017-07-27

    申请号：US15003184

    申请日：2016-01-21

    申请人： YIQUN GE ,  WUXIAN SHI

    发明人： YIQUN GE ,  WUXIAN SHI

    IPC分类号： H03M13/39 ,  H03M13/00 ,  H03M13/29

    CPC分类号： H03M13/3972 ,  H03M13/09 ,  H03M13/13 ,  H03M13/2927 ,  H03M13/616

    摘要： Methods for encoding and decoding Polar codes are provided, together with apparatuses for performing the methods. An encoding method combines first and second sequences of information bits and CRC bits and a plurality of frozen bits into an input vector. The input vector is multiplied by a generator matrix for a Polar code to produce a concatenated codeword. A decoding method receives such a codeword and produces a decoded vector by generating successive levels of a decision tree. For a first number of levels of the decision tree, paths beyond a first maximum number of most probable paths are discarded. For a second number of levels of the decision tree, paths beyond a second maximum number of most probable paths are discarded. In some cases, the decoding method may have improved performance compared to some decoding methods for non-concatenated codewords.

    Method and device for processing received data
    17.
    发明授权
    Method and device for processing received data 有权
    用于处理接收数据的方法和设备

    公开(公告)号：US09559724B2

    公开(公告)日：2017-01-31

    申请号：US14276847

    申请日：2014-05-13

    申请人： CANON KABUSHIKI KAISHA

    发明人： Alain Caillerie ,  Mounir Achir ,  Yacine El Kolli ,  Mickaël Lorgeoux

    IPC分类号： H03M13/11 ,  H03M13/29 ,  H03M13/09

    CPC分类号： H03M13/2915 ,  H03M13/09 ,  H03M13/2927 ,  H03M13/2948

    摘要： A method and device for decoding a plurality of packets of same data. Each packet is encoded using a product code. An encoded packet comprises data blocks is organized into rows and columns. Each of the rows and columns has a respective error detecting code. For a data packet, Erroneous row and column data are detected by their associated error detecting code. In the data packet, a potentially erroneous data block belonging to a row and a column of data blocks both having been detected as erroneous is detected. In another data packet of the same data, a non-erroneous data block corresponding to the identified potentially erroneous data block is determined. The data block is determined as non-erroneous if it belongs to at least one row or column of data having been detected as non-erroneous. The identified potentially erroneous block is replaced with the determined non-erroneous block.

    摘要翻译： 一种用于解码相同数据的多个分组的方法和装置。 每个数据包都使用产品代码进行编码。 编码分组包括数据块被组织成行和列。 每个行和列都有相应的检错代码。 对于数据包，错误的行和列数据由相关的检错码检测。 在数据分组中，检测到属于被检测为错误的一行和一列数据块的潜在错误的数据块。 在相同数据的另一数据分组中，确定与所识别的潜在错误数据块相对应的非错误数据块。 如果数据块属于被检测为非错误的至少一行或一列数据，则将该数据块确定为非错误的。 所识别的潜在错误块被所确定的非错误块替换。

    REMOVING ERROR PATTERNS IN BINARY DATA
    20.
    发明申请
    REMOVING ERROR PATTERNS IN BINARY DATA 有权
    删除二进制数据中的错误模式

    公开(公告)号：US20160126980A1

    公开(公告)日：2016-05-05

    申请号：US14791942

    申请日：2015-07-06

    申请人： International Business Machines Corporation

    发明人： Tobias Blaettler ,  Peter Mueller

    IPC分类号： H03M13/29

    CPC分类号： H03M13/2927 ,  H03M13/2909 ,  H04L1/0057 ,  H04L1/0061

    摘要： A method and a device for removing pathologic error patterns in binary data are proposed. The method comprises the operations of identifying a pathologic error pattern in the binary data, and inverting all bits of the identified pathologic error pattern.

    摘要翻译： 提出了一种用于去除二进制数据中病理错误模式的方法和装置。 该方法包括识别二进制数据中的病理错误模式和反转所识别的病理错误模式的所有位的操作。