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公开(公告)号：US3970941A
公开(公告)日：1976-07-20
申请号：US550320
申请日：1975-02-18
申请人： Horst Leuschner
发明人： Horst Leuschner
CPC分类号： H03K23/50 , H03K23/665 , H03K3/037
摘要： An N-bit programmable divider comprising N "T" flip-flops, N load gates, N-2 enable gates, an output JK flip-flop and a least-significant-bit input inverter; the least-significant-bit flip-flop being enabled by Q of said output flip-flop, the second-least-significant-bit flip-flop being enabled by Q of said least-significant-bit flip-flip, each of said remaining T flip-flops being enabled by NORed Q outputs of all less-significant-bit flip-flops, said output flip-flop having a J input only when the outputs of said N T flip-flops are indicative of a count of 2 and having a K input only with a Q output of said output flip-flop; the divider being loaded by application during Q of the output flip-flop of the complement of the least-significant-bit signal to the clear of the least-significant-bit T flip-flop and higher-significant-bit signals to preset of respective higher-significant-bit T flip-flops.
摘要翻译： 一个N位可编程分频器，包括N“T”个触发器，N个加载门，N-2个使能门，一个输出JK触发器和一个最低有效位输入的反相器; 所述最低有效位触发器由所述输出触发器的Q使能，所述第二最低有效位触发器由所述最低有效位触发器的Q使能，所述剩余 T触发器由所有低有效位触发器的NORed Q输出使能，所述输出触发器仅在所述NT触发器的输出指示计数为2并具有J输入时才具有J输入 K输入仅与所述输出触发器的Q输出; 分频器在最低有效位信号的补码的输出触发器的Q期间通过应用加载，以将最低有效位T触发器和较高有效位信号清除为各自的 较高有效位T触发器。
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公开(公告)号：US3940596A
公开(公告)日：1976-02-24
申请号：US571144
申请日：1975-04-24
CPC分类号： H03K23/44
摘要： Dynamic logic counting circuits are disclosed using recirculating latched memory stages having parallel shift circuits operating in synchronism with the latch circuits to control stepping of the counts. An alternate embodiment employs steering circuit controlled subcounters, each subcounter having a parallel shift circuit operating in synchronism with its respective subcounter to step the next succeeding subcounter when its respective subcounter reaches a predetermined count such as 9 for a binary coded decimal counter or 15 for a binary counter.
摘要翻译： 使用具有与锁存电路同步操作的并行移位电路的再循环锁存存储器级来公开动态逻辑计数电路，以控制计数的步进。 替代实施例采用转向电路控制的子计数器，每个子计数器具有与其各自的子计数器同步操作的并行移位电路，以在其相应的子计数器达到预定的计数时进行下一个后续的子计数器，例如对于二进制编码的十进制计数器为9，或者为 二进制计数器。
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公开(公告)号：US3863224A
公开(公告)日：1975-01-28
申请号：US32794173
申请日：1973-01-30
申请人： GEN ELECTRIC
摘要： A shift register counter, receiving sequentially applied signals, is selectively controllable to divide the signals by selected divide numbers to generate an output signal representative of the input signals divided by a selected divide number.
摘要翻译： 选择性地控制接收顺序施加的信号的移位寄存器计数器，以通过选择的除数对信号进行分频，以产生代表被选择的除法数除以的输入信号的输出信号。
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公开(公告)号：US3584200A
公开(公告)日：1971-06-08
申请号：US3584200D
申请日：1968-02-29
申请人： GEN ELECTRIC
发明人： LAYMAN JOHN D
CPC分类号： B65G43/00 , B65G2811/0673
摘要： An arrangement for using a shift register to represent movement of a monitored item wherein switching of successive stages of the register indicates movement of a predetermined magnitude and wherein interpolation data is also selectively stored in the register to indicate quantities between said predetermined magnitude.
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公开(公告)号：US3573438A
公开(公告)日：1971-04-06
申请号：US3573438D
申请日：1967-07-19
发明人： ROWEN JOHN H
摘要： A shift register includes a plurality of modules connected in parallel, each of the modules comprising a variable resistivity element disposed adjacent to a heating resistor. In order that a pulse propagate from one module to the next, the heating resistor of each module is made responsive to the state of the variable resistivity element of the next preceding module. The shift register has application as a scanner for optoelectronic display panels.
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公开(公告)号：US4193539A
公开(公告)日：1980-03-18
申请号：US849383
申请日：1977-11-07
CPC分类号： H03K5/15093 , H03K23/542
摘要： A timing generator which may be used for multiple-cycle controllers is disclosed. A Johnson counter which may have a selectively operable delay interposed between successive stages is utilized with an oscillator and a plurality of multiplexers to provide a plurality of timing pulse train cycles. Circuitry is provided to eliminate spurious output signals from the timing generator.
摘要翻译： 公开了可用于多循环控制器的定时发生器。 利用振荡器和多个复用器来提供可以在连续级之间插入的选择性可操作延迟的约翰逊计数器来提供多个定时脉冲串循环。 提供电路以消除来自定时发生器的杂散输出信号。
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公开(公告)号：US3987429A
公开(公告)日：1976-10-19
申请号：US631168
申请日：1975-11-11
CPC分类号： G06K13/067
摘要： A malfunction detector system includes sensors spaced along an article flow path. Recirculating shift registers shift a binary 1 signal through succeeding stages as article-detected signals are received from the associated sensors. Logic elements compare the contents of stage "n" of one shift register with the contents of stage "n+1" of the shift register connected to the next sensor on the article flow path. The concurrent existence of binary 1 signals in the compared stages indicates a jam or a sensor failure has occurred.
摘要翻译： 故障检测器系统包括沿着物品流动路径间隔开的传感器。 循环移位寄存器将二进制1信号移动到后续阶段，因为从相关联的传感器接收到物品检测信号。 逻辑元件将一个移位寄存器的阶段“n”的内容与连接到物品流路上的下一个传感器的移位寄存器的“n + 1”阶段的内容进行比较。 在比较的阶段中二进制1信号的并发存在表示卡纸或传感器故障已经发生。
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公开(公告)号：US3983408A
公开(公告)日：1976-09-28
申请号：US458153
申请日：1974-04-05
IPC分类号： G11C19/18 , G11C27/04 , H01L21/33 , H01L21/339 , H01L29/70 , H01L29/762 , G11C19/28 , H03K23/02
CPC分类号： G11C27/04 , G11C19/186
摘要： This invention relates to a bucket brigade circuit or delay line wherein there is provided frequency-dependent compensation of the signal attenuation after n-stages of the circuit. The compensation circuit contains a differential amplifier and a transferring circuit adding the frequency dependent signal loss to the bucket brigade line signal. The differential amplifier samples the signal of two adjacent stages controlled by the same clock signal phase.
摘要翻译： 本发明涉及一种桶式电路或延迟线，其中在电路的n级之后提供对信号衰减的频率相关补偿。 补偿电路包括差分放大器和传送电路，将与频率相关的信号丢失与铲斗旅信号信号相加。 差分放大器对由相同时钟信号相位控制的两个相邻级的信号进行采样。
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19.发明授权TIME-SHARED SHIFT REGISTER COUNTER WITH COUNT MODIFIED EACH Nth RECIRCULATION 失效每共第二次修改的时间共享移位寄存器计数器
公开(公告)号：US3656122A
公开(公告)日：1972-04-11
申请号：US3656122D
申请日：1969-12-11
发明人： PASTERNACK GERALD P
CPC分类号： H04Q3/545 , G06F13/122
摘要： Numbers representing time periods are stored in a plurality of shift registers, each register being associated with a digit of the stored number. Each shift register has a plurality of stages, equal in number to the number of time periods which are served by the counter. The number derived from the output of the shift register is recirculated to the input through an adder, the number count being thereby increased to correspond to elapsed time. The number count is increased, however, only during every nth recirculation to reduce the magnitude of the number which defines an elapsed time period thereby reducing the number of shift registers required.
摘要翻译： 表示时间段的数字被存储在多个移位寄存器中，每个寄存器与存储号码的数字相关联。 每个移位寄存器具有与计数器所服务的时间段数相等的多个级。 从移位寄存器的输出得到的数字通过加法器再循环到输入端，从而增加数量以对应于经过的时间。 然而，仅在每第n次再循环期间才增加数量计数，以减小定义经过时间段的数量的大小，从而减少所需的移位寄存器的数量。
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公开(公告)号：US3609311A
公开(公告)日：1971-09-28
申请号：US3609311D
申请日：1969-05-26
发明人： WAYNE RONALD G
CPC分类号： H03K23/66
摘要： A coincident counting system is described which comprises a plurality of ring counters, each ring counter having dissimilar number of bit stages. Each initial bit stage of each ring counter is only coincident on each full cycle of operation, thereby indicating maximum count. By proper selection logic, coincidence of each bit in each register may be selected to vary the count. A single input switch increments all ring counters simultaneously until selected coincidence occurs.
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