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17 条记录 (耗时 0.017 秒)

    NEURAL NETWORK SYSTEM WITH NEURONS INCLUDING CHARGE-TRAP TRANSISTORS AND NEURAL INTEGRATORS AND METHODS THEREFOR
    11.
    发明公开
    NEURAL NETWORK SYSTEM WITH NEURONS INCLUDING CHARGE-TRAP TRANSISTORS AND NEURAL INTEGRATORS AND METHODS THEREFOR 审中-公开

    公开(公告)号：US20240028884A1

    公开(公告)日：2024-01-25

    申请号：US18255346

    申请日：2021-10-04

    申请人： The Regents of the University of California

    发明人： Steven L. MORAN ,  Subramanian S. IYER ,  Zhe WAN ,  Sudhakar PAMARTI

    IPC分类号： G06N3/065 ,  H01L29/792 ,  H10B43/00

    CPC分类号： G06N3/065 ,  H01L29/792 ,  H10B43/00

    摘要： Present implementations can include a system with a transistor array including a plurality of charge-trap transistors, the charge-trap transistors being operatively coupled with corresponding input nodes, and a neural integrator including a first integrator node and a second integrator node operatively coupled with the transistor array, and generating an output corresponding to a neuron of a neural network system. Present implementations can include a neural integrator with a first integrator node operatively coupled with a first charge-trap transistor of a transistor array, a second integrator node operatively coupled with a second charge-trap transistor of the transistor array, the second charge-trap transistor being operatively coupled with the first charge-trap transistor, and a capacitor operatively coupled with the first integrator node and the second integrator node, and operable to generate an output based on a first voltage at the first integrator node and a second voltage at the second integrator node.

    Operation method of multi-bits read only memory
    12.
    发明授权
    Operation method of multi-bits read only memory 有权

    公开(公告)号：US11837299B2

    公开(公告)日：2023-12-05

    申请号：US17716122

    申请日：2022-04-08

    申请人： Chen-Feng Chang

    发明人： Chen-Feng Chang ,  Tien-Sheng Chao

    IPC分类号： G11C16/04 ,  G11C17/12 ,  G11C11/56 ,  H10B20/20 ,  H10B43/00

    CPC分类号： G11C17/12 ,  G11C11/5671 ,  G11C16/0466 ,  H10B20/20 ,  H10B43/00

    摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode, a first oxide located between the first electrode and the conductive gate, and a second oxide located between the second electrode and the conductive gate. The present invention creates an initial state wherein the transistor structure is not conducting, an intermediate state wherein the first oxide is punched through by the first voltage, and a fully opened state wherein both the first oxide and the second oxide are punched through. The aforementioned states allow storage of multiple bits on the read only memory.

    Vertical semiconductor devices
    16.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US11925020B2

    公开(公告)日：2024-03-05

    申请号：US17473006

    申请日：2021-09-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： Shinhwan Kang ,  Younghwan Son ,  Haemin Lee ,  Kohji Kanamori ,  Jeehoon Han

    IPC分类号： H10B43/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    CPC分类号： H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

    摘要： A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

    SEMICONDUCTOR DEVICE
    17.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240047579A1

    公开(公告)日：2024-02-08

    申请号：US18199504

    申请日：2023-05-19

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Seonhaeng LEE

    IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/22 ,  H01L21/762 ,  H10B12/00 ,  H10B41/00 ,  H10B43/00

    CPC分类号： H01L29/7833 ,  H01L21/76898 ,  H01L21/22 ,  H01L21/762 ,  H01L21/76832 ,  H10B12/30 ,  H10B41/00 ,  H10B43/00

    摘要： A semiconductor device includes a substrate including first and second surfaces opposing each other. A device isolation layer extends through the substrate and defines an active region in the substrate. A gate electrode is on the first surface of the substrate. A wiring structure electrically connects the gate electrode and the active region. The active region includes a target doped region between the device isolation layer and the gate electrode and including a dopant having a first concentration. A path doped region is between the device isolation layer and the gate electrode and extends from the second surface of the substrate to the target doped region. The path doped region includes a dopant having a second concentration less than the first concentration. The target doped region and the path doped region are formed by implanting the dopant through the second surface of the substrate.