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    EVALUATION OF BACKGROUND LEAKAGE TO SELECT WRITE VOLTAGE IN MEMORY DEVICES
    12.
    发明公开
    EVALUATION OF BACKGROUND LEAKAGE TO SELECT WRITE VOLTAGE IN MEMORY DEVICES 审中-公开

    公开(公告)号：US20240331781A1

    公开(公告)日：2024-10-03

    申请号：US18744335

    申请日：2024-06-14

    申请人： Micron Technology, Inc.

    发明人： Nevil N. Gajera ,  Karthik Sarpatwari ,  Zhongyuan Lu

    IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

    CPC分类号： G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3459

    摘要： Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.

    Multi-step pre-read for write operations in memory devices
    14.
    发明授权
    Multi-step pre-read for write operations in memory devices 有权

    公开(公告)号：US12106803B2

    公开(公告)日：2024-10-01

    申请号：US17824776

    申请日：2022-05-25

    申请人： Micron Technology, Inc.

    发明人： Yen Chun Lee ,  Nevil N. Gajera ,  Karthik Sarpatwari

    IPC分类号： G11C11/4074 ,  G11C13/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0057 ,  G11C2013/0076

    摘要： Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

    MEMORY DEVICE AND METHOD
    15.
    发明公开
    MEMORY DEVICE AND METHOD 审中-公开

    公开(公告)号：US20240321362A1

    公开(公告)日：2024-09-26

    申请号：US18596541

    申请日：2024-03-05

    申请人： Kioxia Corporation

    发明人： Hideki IGARASHI ,  Takaya IZUMI

    IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/34

    CPC分类号： G11C16/102 ,  G11C16/0433 ,  G11C16/3404

    摘要： A memory device includes first and second strings including transistors, a first wiring connected to the first string, a second wiring connected to the second string, a third wiring connected to both strings, and a circuit for executing a write operation on a first transistor of the first string and a second transistor of the second string. The operation includes a first operation by which a first voltage is applied to the wirings and a second operation by which a second voltage is applied to gates of the first and second transistors. When a current flows between the first and third wirings but does not flow between the second and third wirings in the first operation, the circuit causes a third voltage to be applied to the first wiring, and causes a fourth voltage higher than the third voltage to be applied to the second wiring in the second operation.