公开(公告)号：US11888493B2

公开(公告)日：2024-01-30

申请号：US18083396

申请日：2022-12-16

Applicant: Skyworks Solutions, Inc.

Inventor： Timothy Adam Monk ,  Douglas F. Pastorello ,  Krishnan Balakrishnan ,  Raghunandan Kolar Ranganathan

IPC: H03M1/10 ,  G04F10/00 ,  H03L7/085

CPC classification number: H03M1/1014 ,  G04F10/005 ,  H03L7/085

Abstract: A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

公开(公告)号：US20240030926A1

公开(公告)日：2024-01-25

申请号：US17873129

申请日：2022-07-25

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman

IPC: H03L7/085 ,  H03L7/083 ,  H03L7/107 ,  H03L7/08

CPC classification number: H03L7/085 ,  H03L7/083 ,  H03L7/1072 ,  H03L7/0807

Abstract: In described examples, a retimer includes a reference voltage generator, first, second, third, and fourth comparators, a hit sensor, a window results comparison circuit, and a window control circuit. First inputs of the first, second, third, and fourth comparators receive samples of a data stream. First, second, third, and fourth outputs of the reference voltage generator are coupled to respective second inputs of the first, second, third, and fourth comparators. The third and fourth comparators output to, respectively, first and second inputs of the hit sensor. The hit sensor outputs to an input of the window results comparison circuit. The window results comparison circuit outputs to an input of the window control circuit. The window control circuit outputs to an input of the reference voltage generator.

公开(公告)号：US11881864B2

公开(公告)日：2024-01-23

申请号：US17739197

申请日：2022-05-09

Applicant: Realtek Semiconductor Corp.

Inventor： Yu-Che Yang

IPC: H03L7/085 ,  H03L7/099

CPC classification number: H03L7/085 ,  H03L7/0991 ,  H03L2207/50

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.

公开(公告)号：US20240022253A1

公开(公告)日：2024-01-18

申请号：US18136017

申请日：2023-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Venkatasuryam Setty ISSA ,  Aswani Aditya Kumar TADINADA ,  Subba Reddy SIDDAMURTHY

IPC: H03L7/081 ,  H03L7/099 ,  H03L7/18 ,  H03L7/085

CPC classification number: H03L7/081 ,  H03L7/099 ,  H03L7/18 ,  H03L7/085

Abstract: There is provided a method for generating a select signal for a multiplexer of a Multiplying Delay Locked Loop (MDLL). The method includes determining that an output of a divider of the MDLL is a high level, determining that an output signal of a multiplexed voltage controlled oscillator (VCO) of the MDLL is a falling edge after the output of the divider is the high level and inserting a select signal as a select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO in response to determining that the output of the divider has achieved the high level.

公开(公告)号：US20240019891A1

公开(公告)日：2024-01-18

申请号：US18446869

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Wei Chih Chen

IPC: G06F1/08 ,  H03L7/085 ,  H03M1/66 ,  H03K19/21 ,  H03L7/099

CPC classification number: G06F1/08 ,  H03L7/085 ,  H03M1/66 ,  H03K19/21 ,  H03L7/0998

Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

公开(公告)号：US20240014823A1

公开(公告)日：2024-01-11

申请号：US18348009

申请日：2023-07-06

Applicant: Winbond Electronics Corp.

Inventor： Shinya OKUNO

IPC: H03L7/081 ,  H03L7/085 ,  G11C11/4093 ,  G11C11/4076

CPC classification number: H03L7/0812 ,  H03L7/085 ,  G11C11/4093 ,  G11C11/4076

Abstract: A delay control circuit provided herein includes a DLL control circuit, a delay line circuit, and an N-value detection circuit. The DLL control circuit determines the delay amount based on the phase difference between the input and output clock signals. The delay line circuit delays the input clock signal based on the delay amount to generate an output clock signal. The N-value detection circuit performs an N-value detection operation for detecting the number of delayed clock cycles from the input clock signal to the output clock signal. When it is determined to be in an overflow state, the DLL control circuit outputs a signal indicating an overflow state to the N-value detection circuit. When the signal indicating the overflow state is received, the N-value detection circuit does not perform the N-value detection operation, but instead sets the number of delayed clock cycles to a predetermined value.

公开(公告)号：US11863192B2

公开(公告)日：2024-01-02

申请号：US17855537

申请日：2022-06-30

Applicant: Silicon Laboratories Inc.

Inventor： John M. Khoury

IPC: H03L7/099 ,  H03L7/085 ,  G06F1/02 ,  H03B5/12 ,  H03L7/14 ,  H03L7/189 ,  H03L7/197

CPC classification number: H03L7/0991 ,  G06F1/022 ,  H03B5/1206 ,  H03B5/1212 ,  H03B5/1218 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0992 ,  H03L7/148 ,  H03L7/189 ,  H03L7/1974

Abstract: An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.

公开(公告)号：US20230393610A1

公开(公告)日：2023-12-07

申请号：US18455101

申请日：2023-08-24

Applicant: International Business Machines Corporation

Inventor： Douglas J. Malone ,  Andreas H. A. Arp ,  Franklin M. Baez ,  Daniel M. Dreps ,  Jason Lee Frankel ,  Chad Andrew Marquart ,  Ching Lung Tong ,  Lily Jielu Zhang

IPC: G06F1/12 ,  H03L7/085 ,  G06F1/08

CPC classification number: G06F1/12 ,  H03L7/085 ,  G06F1/08

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

公开(公告)号：US11838027B2

公开(公告)日：2023-12-05

申请号：US17869784

申请日：2022-07-20

Applicant: Realtek Semiconductor Corp.

Inventor： Yu-Che Yang

IPC: H03L7/099 ,  H03L7/085 ,  H03L7/107

CPC classification number: H03L7/0991 ,  H03L7/085 ,  H03L7/107 ,  H03L2207/50

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.

公开(公告)号：US20230378961A1

公开(公告)日：2023-11-23

申请号：US18115682

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Bhavesh G. Bhakta ,  Venkateswara Reddy Pothireddy ,  Abhijit Kumar Das

IPC: H03L7/081 ,  H03L7/085

CPC classification number: H03L7/0818 ,  H03L7/0816 ,  H03L7/0814 ,  H03L7/085

Abstract: An example apparatus includes: digitally locked loop (DLL) circuitry coupled to a clock terminal and configured to generate a plurality of delayed clocks at a plurality of delayed clock terminals based on a reference clock of the clock terminal; first retimer circuitry coupled to the plurality of delayed clock terminals, a first data terminal, and a second data terminal, the first retimer circuitry configured to delay and serialize data of the first data terminal and the second data terminal using at least one of the delayed clocks of the plurality of delayed clock terminals; and second retimer circuitry coupled to the plurality of delayed clock terminals, a third data terminal, and a fourth data terminal, the second retimer circuitry configured to delay and serialize data of the third data terminal and the fourth data terminal.