公开(公告)号：US11677000B2

公开(公告)日：2023-06-13

申请号：US17450186

申请日：2021-10-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01Q1/22

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01Q1/2283

Abstract: An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.

公开(公告)号：US11675046B2

公开(公告)日：2023-06-13

申请号：US16558095

申请日：2019-08-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： See Taur Lee ,  Sher Jiung Fang

IPC: G01S7/35 ,  H03K5/00 ,  H03F3/24 ,  G01S7/282

CPC classification number: G01S7/35 ,  G01S7/282 ,  H03F3/245 ,  H03K5/00006 ,  H03F2200/451

Abstract: Transmitters having increased efficiency, such as may be useful in millimeter-wave devices. A semiconductor device, comprising a transmitter, comprising a modulator configured to receive a differential input signal having a first frequency and provide a differential modulated signal having the first frequency and a first clock phase; a series comprising one or more frequency multipliers, wherein the series of frequency multipliers is configured to receive the differential modulated signal and provide a differential second signal having a second frequency greater than the first frequency and having a second clock phase; and an output transformer configured to receive the differential second signal and transform the differential second signal to a single-ended output signal. Methods of using such transmitters. Systems for manufacturing devices comprising such transmitters.

公开(公告)号：US11664470B2

公开(公告)日：2023-05-30

申请号：US17863922

申请日：2022-07-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran Krishnasamy ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Ramsey Hazbun

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/103 ,  H01L31/028

CPC classification number: H01L31/035281 ,  H01L31/028 ,  H01L31/02327 ,  H01L31/103 ,  H01L31/1808

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

公开(公告)号：US11664432B2

公开(公告)日：2023-05-30

申请号：US16556796

申请日：2019-08-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Dirk Utess ,  Zhixing Zhao ,  Dominik M. Kleimaier ,  Irfan A. Saadat ,  Florent Ravaux

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L27/092 ,  H01L29/401 ,  H01L29/7845

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

公开(公告)号：US11662523B2

公开(公告)日：2023-05-30

申请号：US17151955

申请日：2021-01-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Roderick A. Augur ,  Kenneth J. Giewont ,  Karen Nummy

IPC: G02B6/30 ,  G02B6/42 ,  F21V8/00 ,  G02B6/12

CPC classification number: G02B6/305 ,  G02B6/0046 ,  G02B6/4298 ,  G02B6/12002 ,  G02B6/12004 ,  G02B2006/12147

Abstract: Structures including an edge coupler and methods of forming a structure including an edge coupler. The structure includes a waveguide core over a dielectric layer and a back-end-of-line stack over the dielectric layer and the waveguide core. The back-end-of-line stack includes a side edge and a truncated layer that is overlapped with a tapered section of the waveguide core. The truncated layer has a first end surface adjacent to the side edge and a second end surface above the tapered section of the waveguide core. The truncated layer is tapered from the first end surface to the second end surface.

公开(公告)号：US20230163134A1

公开(公告)日：2023-05-25

申请号：US17533402

申请日：2021-11-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

IPC: H01L27/12

CPC classification number: H01L27/1207

Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

公开(公告)号：US11658053B2

公开(公告)日：2023-05-23

申请号：US16659090

申请日：2019-10-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael Raga-Barone

IPC: H01L21/677 ,  G03F7/20

CPC classification number: H01L21/67769 ,  G03F7/70741 ,  H01L21/67775

Abstract: One illustrative device disclosed herein includes a FOUP (Front Opening Unified Pod) storage bin, a plurality of pins positioned on a first surface of the FOUP storage bin, wherein the plurality of pins are adapted to engage and register with the FOUP, and a conversion plate. In one illustrative embodiment, the conversion plate includes a plate with a front surface and a back surface, a reticle pod receiving structure on the front surface that at least partially bounds a reticle pod receiving area on the front surface, and a pin engagement structure on the back side that is adapted to engage the plurality of pins on the first surface of the FOUP storage bin.

公开(公告)号：US11656409B2

公开(公告)日：2023-05-23

申请号：US17197133

申请日：2021-03-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Qizhi Liu

IPC: G02B6/124 ,  G02B6/13

CPC classification number: G02B6/124 ,  G02B6/13

Abstract: Embodiments of the disclosure provide an optical antenna for a photonic integrated circuit (PIC). The optical antenna includes a semiconductor waveguide on a semiconductor layer. The semiconductor waveguide includes a first vertical sidewall over the semiconductor layer over the semiconductor layer. A plurality of grating protrusions extends horizontally from the first vertical sidewall of the semiconductor waveguide.

公开(公告)号：US11652069B2

公开(公告)日：2023-05-16

申请号：US17114894

申请日：2020-12-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ranjan Rajoo ,  Frank G. Kuechenmeister ,  Dirk Breuer

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78

Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.

公开(公告)号：US20230147981A1

公开(公告)日：2023-05-11

申请号：US18149239

申请日：2023-01-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/76 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7606 ,  H01L29/0847 ,  H01L29/1033

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.