公开(公告)号：US20240088885A1

公开(公告)日：2024-03-14

申请号：US18370582

申请日：2023-09-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Jean-Michel SIMONNET ,  Fabrice GUITTON

IPC: H03K17/0812

CPC classification number: H03K17/0812 ,  H02P27/04

Abstract: A control circuit for controlling a first transistor includes a diode for suppressing transient voltages. A cathode of the diode is coupled to a first conduction terminal of the first transistor, and an anode of the diode is coupled to a first node. A first resistor is coupled between the first node and a control terminal of the first transistor. A second transistor has a control terminal coupled to the first node, a first conduction terminal configured to receive a first supply voltage, and a second conduction terminal coupled to the control terminal of the first transistor.

公开(公告)号：US11923234B2

公开(公告)日：2024-03-05

申请号：US16950787

申请日：2020-11-17

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/56 ,  H01L21/762 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L21/76224 ,  H01L21/0228 ,  H01L21/56

Abstract: The present disclosure relates to a method for manufacturing electronic chips. The method includes forming a plurality of trenches on a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed. The trenches delimit laterally a plurality of chips, and each of the chips includes a single integrated circuit. The method further includes electrically isolating flanks of each of the chips by forming an electrically isolating layer on lateral walls of the trenches.

公开(公告)号：US11909427B2

公开(公告)日：2024-02-20

申请号：US18113796

申请日：2023-02-24

Applicant: STMicroelectronics (Tours) SAS

Inventor： Jean Pierre Proot ,  Pascal Paillet ,  Francois Dupont

IPC: H04B1/04 ,  H03H7/38 ,  H04B1/18

CPC classification number: H04B1/0458 ,  H03H7/38 ,  H04B1/18

Abstract: A circuit device includes a directional coupler with a first port receiving a radiofrequency signal, a second port outputting a signal in response to signal received by the first port, and a third port outputting a signal in response to a reflection of the signal at the second port. An impedance matching network is connected between the second port and an antenna. The impedance matching network includes fixed inductive and capacitive components and a single variable inductive or capacitive component. A diode coupled to the third port of the coupler generates a voltage at a measurement terminal which is processed in order to select and set the inductance or capacitance value of the variable inductive or capacitive component.

公开(公告)号：US20230402644A1

公开(公告)日：2023-12-14

申请号：US18335927

申请日：2023-06-15

Applicant: STMicroelectronics (Tours) SAS

Inventor： Séverin LARFAILLOU ,  Delphine GUY-BOUYSSOU

IPC: H01M10/052 ,  H01M10/44 ,  H01M10/0585 ,  H01M4/38 ,  H01M4/40 ,  H01M4/04 ,  H01M4/134 ,  H01M4/1395 ,  H01M10/0562

CPC classification number: H01M10/052 ,  H01M10/44 ,  H01M10/0585 ,  H01M4/38 ,  H01M4/405 ,  H01M4/0445 ,  H01M4/134 ,  H01M4/1395 ,  H01M10/0562 ,  H01M4/382

Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.

公开(公告)号：US11810911B2

公开(公告)日：2023-11-07

申请号：US16897205

申请日：2020-06-09

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMICROELECTRONICS (TOURS) SAS

Inventor： Mathieu Rouviere ,  Arnaud Yvon ,  Mohamed Saadna ,  Vladimir Scarpa

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/872

CPC classification number: H01L27/0629 ,  H01L21/0254 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/872

Abstract: A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

公开(公告)号：US11784104B2

公开(公告)日：2023-10-10

申请号：US17491189

申请日：2021-09-30

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier Ory ,  Romain Jaillet

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L29/861

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/78 ,  H01L29/861

Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

公开(公告)号：US20230275526A1

公开(公告)日：2023-08-31

申请号：US18144639

申请日：2023-05-08

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frederic GAUTIER

IPC: H02M7/219 ,  H02M7/5387 ,  G05F3/20 ,  H02M7/217

CPC classification number: H02M7/219 ,  H02M7/5387 ,  G05F3/20 ,  H02M7/217 ,  H02M1/0032

Abstract: A rectifying element includes a MOS transistor series-connected with a Schottky diode. A bias voltage is applied between the control terminal of the MOS transistor and the terminal of the Schottky diode opposite to the transistor. A pair of the rectifying elements are substituted for diodes of a rectifying bridge circuit. Alternatively, the control terminal bias is supplied from a cross-coupling against the Schottky diodes. In another implementation, the Schottky diodes are omitted and the bias voltage applied to control terminals of the MOS transistors is switched in response to cross-coupled divided source-drain voltages of the MOS transistors. The circuits form components of a power converter.

公开(公告)号：US20230215733A1

公开(公告)日：2023-07-06

申请号：US18148329

申请日：2022-12-29

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3086 ,  H01L21/30604

Abstract: The present description concerns a method of forming a cavity in a substrate comprising: the forming of an etch mask comprising, opposite the location of the cavity, a plurality of sets of openings, the ratio between the openings and the mask of each set being selected according to the desired profile of the cavity opposite the surface of the mask having the set inscribed therein; and the wet etching of the substrate through the openings.

公开(公告)号：US11664367B2

公开(公告)日：2023-05-30

申请号：US17717501

申请日：2022-04-11

Applicant: STMicroelectronics (Tours) SAS

Inventor： Patrick Poveda

IPC: H02H9/00 ,  H01L27/02 ,  H01L29/87 ,  H01L29/66 ,  H01L23/60 ,  H01L29/78 ,  H01L29/788 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/06 ,  H01L29/866 ,  H02H9/04 ,  H03H11/04

CPC classification number: H01L27/0248 ,  H01L23/528 ,  H01L23/5227 ,  H01L23/60 ,  H01L27/0255 ,  H01L27/0676 ,  H01L29/0649 ,  H01L29/66113 ,  H01L29/7808 ,  H01L29/7821 ,  H01L29/7886 ,  H01L29/866 ,  H01L29/87 ,  H02H9/046 ,  H03H11/04

Abstract: A protection device includes a first inductive element connecting first and second terminals and a second inductive element connecting third and fourth terminals. A first component includes a first avalanche diode connected in parallel with a first diode string, anodes of the first avalanche diode and a last diode in the string being connected to ground, cathodes of the first avalanche diode and a first diode in the string being connected, and a tap of the first diode string being connected to the first terminal. A second protection component includes a second avalanche diode connected in parallel with a second diode string, anodes of the second avalanche diode and a last diode in the string being connected to ground, cathodes of the second avalanche diode and a first diode in the string being connected, and a tap of the second diode string being connected to the third terminal.

公开(公告)号：US11532616B2

公开(公告)日：2022-12-20

申请号：US16709753

申请日：2019-12-10

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Aurelie Arnaud

IPC: H01L27/07 ,  H01L27/02 ,  H01L21/265 ,  H01L21/266

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.