公开(公告)号：US20060126595A1

公开(公告)日：2006-06-15

申请号：US11012372

申请日：2004-12-14

Applicant: Claus Dahm ,  Hisham Abdelhamid ,  Joseph Stone ,  Rajesh Kumar

Inventor： Claus Dahm ,  Hisham Abdelhamid ,  Joseph Stone ,  Rajesh Kumar

IPC: H04L12/56 ,  H04L12/26 ,  H04L12/28 ,  G01R31/08 ,  H04L12/66 ,  H04L1/00

CPC classification number: H04L29/06027 ,  H04L41/12 ,  H04L45/00 ,  H04L45/22 ,  H04L65/1026 ,  H04L65/1036 ,  H04L65/1043 ,  H04L65/1069 ,  H04L69/24

Abstract: A method and system for establishing a call between two endpoints residing on different media gateways in a decomposed voice over packet architecture. Cluster attributes identifying alternate bearer possibilities are exchanged between media gateways as part of capabilities negotiation which occurs during call setup conducted by an external call control element over a core network. The media gateways analyze the cluster attributes to determine whether bearer possibilities exist apart from the core network. If an alternate bearer possibility exists, the alternate is employed and the call is established via the alternate bearer directly between the media gateways, thus bypassing the core network.

Abstract translation: 一种用于通过分组架构在分解的语音中驻留在不同媒体网关上的两个端点之间建立呼叫的方法和系统。 识别替代承载可能性的集群属性在媒体网关之间交换，作为在由外部呼叫控制元件通过核心网络进行的呼叫建立期间发生的能力协商的一部分。 媒体网关分析集群属性，以确定承载可能性是否存在于核心网络之外。 如果存在替代承载可能性，则采用备用，并且通过直接在媒体网关之间的替代承载来建立呼叫，从而绕过核心网络。

公开(公告)号：US20050145852A1

公开(公告)日：2005-07-07

申请号：US10995566

申请日：2004-11-24

Applicant: Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L29/80 ,  H01L21/337 ,  H01L29/24 ,  H01L29/808 ,  H01L29/15

CPC classification number: H01L29/8083 ,  H01L29/1608

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

Abstract translation: 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

公开(公告)号：US06853006B2

公开(公告)日：2005-02-08

申请号：US10630978

申请日：2003-07-31

Applicant: Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

Inventor： Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC: H01L29/80 ,  H01L21/04 ,  H01L21/337 ,  H01L29/04 ,  H01L29/24 ,  H01L29/808 ,  H01L31/312

CPC classification number: H01L29/66068 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/8083

Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is . A trench is formed on the SiC to have a stripe structure extending toward a direction. An SiC epitaxial layer is formed on an inside surface of the trench.

Abstract translation: 碳化硅（SiC）衬底设置有离轴取向{0001}表面，其离轴方向<11-20>。 在SiC上形成沟槽以具有向<11-20>方向延伸的条纹结构。 在沟槽的内表面上形成SiC外延层。

公开(公告)号：US20050006716A1

公开(公告)日：2005-01-13

申请号：US10776338

申请日：2004-02-12

Applicant: Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

Inventor： Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

IPC: H01L21/04 ,  H01L21/337 ,  H01L21/8232 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/07 ,  H01L27/088 ,  H01L27/095 ,  H01L29/24 ,  H01L29/80 ,  H01L29/808 ,  H01L29/00

CPC classification number: H01L29/66068 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/1608 ,  H01L29/808 ,  H01L29/8083

Abstract: A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field effect transistor connects to the source of the first field effect transistor. The gate of the second field effect transistor connects to the gate of the first field effect transistor.

Abstract translation: 半导体器件包括：第一场效应晶体管，其包括源极和栅极，并设置在碳化硅衬底中; 以及包括漏极和栅极并设置在所述衬底中的第二场效应晶体管。 第二场效应晶体管的漏极连接到第一场效应晶体管的源极。 第二场效应晶体管的栅极连接到第一场效应晶体管的栅极。

公开(公告)号：US06824822B2

公开(公告)日：2004-11-30

申请号：US09942631

申请日：2001-08-31

Applicant: Michael E. Rickey ,  J. Michael Ramstack ,  Rajesh Kumar

Inventor： Michael E. Rickey ,  J. Michael Ramstack ,  Rajesh Kumar

IPC: B01J1312

CPC classification number: A61K38/09 ,  A61K9/1641 ,  A61K9/1647 ,  A61K9/1682 ,  A61K9/1694 ,  A61K9/5089 ,  A61K31/519 ,  B01J8/025 ,  B01J13/08 ,  B01J13/12 ,  B01J13/206 ,  B01J14/00 ,  B01J19/121 ,  B01J19/122 ,  B01J19/2415 ,  B01J2219/0877

Abstract: Methods for preparing microparticles having reduced residual solvent levels. Microparticles are contacted with a non-aqueous washing system to reduce the level of residual solvent in the microparticles. Preferred non-aqueous washing systems include 100% ethanol and a blend of ethanol and heptane. A solvent blend of a hardening solvent and a washing solvent can be used to harden and wash microparticles in a single step, thereby eliminating the need for a post-hardening wash step.

Abstract translation: 制备具有降低的残留溶剂水平的微粒的方法。 微粒与非水洗涤体系接触以降低微粒中残留溶剂的含量。 优选的非水洗涤系统包括100％乙醇和乙醇与庚烷的混合物。 可以使用硬化溶剂和洗涤溶剂的溶剂共混物在一个步骤中硬化和洗涤微粒，从而不需要后硬化洗涤步骤。

公开(公告)号：US06576929B2

公开(公告)日：2003-06-10

申请号：US10135522

申请日：2002-05-01

Applicant: Rajesh Kumar ,  Takamasa Suzuki

Inventor： Rajesh Kumar ,  Takamasa Suzuki

IPC: H01K2978

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/8083

Abstract: A channel layer 4 is formed on an n−-type epitaxial layer 2 and first gate areas 3, and field enhanced area(s) 5 and second gate areas 6 are formed on the first gate areas 3. Furthermore, n+-type source areas 7 and a third gate area 8 are formed on the second gate areas 6. These steps result in a device structure having a first J-FET with the n+-type source areas 7 and the n+-type substrate 1 as a source and drain and the first gate areas 3 at the right and left in the figure as a gate; and the second J-FET with the n+-type source areas 7 and the n+-type substrate 1 as a source and drain and the second gate areas 6 and the third gate area 8 as a gate. The first J-FET is normally-on, while the second J-FET is normally-off.

公开(公告)号：US06573534B1

公开(公告)日：2003-06-03

申请号：US09265582

申请日：1999-03-10

Applicant: Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

Inventor： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

IPC: H01L310312

CPC classification number: H01L29/7828 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7838 ,  Y10S438/931

Abstract: A semiconductor device, comprising: a semiconductor substrate comprising silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type; a first semiconductor region formed on the semiconductor substrate and comprising silicon carbide of a second conductivity type; a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the semiconductor substrate of the first conductivity type by the first semiconductor region; a third semiconductor region formed on the semiconductor region, connected to the semiconductor substrate and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the semiconductor substrate; and a gate electrode formed on the third semiconductor region via an insulating layer; wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said semiconductor device has a normally OFF characteristic.

Abstract translation: 一种半导体器件，包括：包含第一导电类型的碳化硅的半导体衬底; 第一导电类型的碳化硅外延层; 形成在所述半导体衬底上并且包括第二导电类型的碳化硅的第一半导体区域; 形成在所述第一半导体区域上的第二半导体区域，包括所述第一导电类型的碳化硅并且通过所述第一半导体区域与所述第一导电类型的半导体衬底分离; 形成在所述半导体区域上的第三半导体区域，与所述半导体衬底和所述第二半导体区域连接，所述第二半导体区域包括所述第一导电型的碳化硅，并且具有比所述半导体衬底更高的电阻; 以及经由绝缘层形成在所述第三半导体区域上的栅电极; 其中当没有电压施加到所述栅电极时，所述第三半导体层被耗尽，使得所述半导体器件具有正常OFF特性。

公开(公告)号：US6137775A

公开(公告)日：2000-10-24

申请号：US1827

申请日：1997-12-31

Applicant: Merwyn C. Bartlett ,  Rajesh Kumar ,  David G. Way

Inventor： Merwyn C. Bartlett ,  Rajesh Kumar ,  David G. Way

IPC: H04Q3/00 ,  G01R31/08

CPC classification number: H04Q3/0079

Abstract: A spare capacity planning tool for planning spare capacity in a transport network during a multiple-span failure following a single failure event. The spare capacity planning tool simulates restoration of a transport network regardless of the sequence of failures. The system and method utilize a permutation reducer to minimize the number of sequences to be verified during simulated or actual restoration activities. The permutation reducer reduces the number of sequences to to during simulated restoration activities to a first order function rather than a factorial function of the number of failed spans.

Abstract translation: 一个备用容量规划工具，用于在单个故障事件发生的多级故障期间规划传输网络中的备用容量。 备用容量规划工具模拟传输网络的恢复，而不管故障顺序如何。 该系统和方法利用置换减少器来最小化在模拟或实际恢复活动期间要验证的序列的数量。 排列减少器将在模拟恢复活动期间的序列数减少到一阶函数，而不是失败跨度数量的阶乘函数。

公开(公告)号：US6057558A

公开(公告)日：2000-05-02

申请号：US34344

申请日：1998-03-04

Applicant: Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

Inventor： Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L31/0312

CPC classification number: H01L29/0847 ,  H01L29/0626 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7828 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238

Abstract: In a silicon carbide semiconductor device such as a trench gate type power MOSFET, the film thickness and the impurity concentration of a thin film silicon carbide semiconductor layer formed on a trench side face to constitute an accumulation-type channel-forming region and enable the device to operate with a low gate voltage, low on-resistance and low power loss are set so that on impression of a reverse bias voltage a pn junction between a P-type epitaxial layer and an n.sup.- -type epitaxial layer undergoes avalanche breakdown before the thin film silicon carbide semiconductor layer undergoes punch-through. By this means it is possible to obtain a target high source-drain withstand voltage.

Abstract translation: 在诸如沟槽栅型功率MOSFET的碳化硅半导体器件中，形成在沟槽侧面上的薄膜碳化硅半导体层的膜厚度和杂质浓度构成积聚型沟道形成区域，并使器件 以低栅极电压操作，设置低导通电阻和低功率损耗，使得在反向偏置电压的印象上，P型外延层和n型外延层之间的pn结在其之前经历雪崩击穿 薄膜碳化硅半导体层进行穿通。 通过这种方式，可以获得目标高的源极 - 漏极耐受电压。

公开(公告)号：US6054752A

公开(公告)日：2000-04-25

申请号：US107507

申请日：1998-06-30

Applicant: Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

Inventor： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/34 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0611 ,  H01L29/0638 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/1608

Abstract: A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.

Abstract translation: 半导体器件包括：半导体衬底，包括形成在第一半导体层上的第一导电型第一半导体层和第二导电型第二半导体层。 在半导体衬底中形成用于控制在源电极和漏电极之间流动的电流的单元。 在单电池的周边区域形成沟槽，形成台面结构。 在第二沟槽的侧面上的绝缘膜与第一半导体层和第二半导体层之间形成场弛豫层，以使绝缘膜中的电场的集中化。