公开(公告)号：US20230420520A1

公开(公告)日：2023-12-28

申请号：US18150524

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han Chuang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kai-Lin Chuang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/775

Abstract: In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.

公开(公告)号：US11855084B2

公开(公告)日：2023-12-26

申请号：US17856471

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

公开(公告)号：US11854908B2

公开(公告)日：2023-12-26

申请号：US17662569

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Shi Ning Ju ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823878 ,  H01L21/02603 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

公开(公告)号：US20230411219A1

公开(公告)日：2023-12-21

申请号：US18151598

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L21/823857 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L21/823807 ,  H01L29/66439 ,  H01L29/6684 ,  H01L29/4908

Abstract: A semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; a second gate dielectric layer disposed over the second channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and the second gate dielectric layer includes a second dipole dopant embedded therein. A boundary between the first gate dielectric layer and the second gat dielectric layer contains the first dipole dopant and the second dipole dopant.

公开(公告)号：US11848372B2

公开(公告)日：2023-12-19

申请号：US17236675

申请日：2021-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/7851

Abstract: A method provides a structure having a fin oriented lengthwise and widthwise along first and second directions respectively, an isolation structure adjacent to sidewalls of the fin, and first and second source/drain (S/D) features over the fin. The method includes forming an etch mask exposing a first portion of the fin under the first S/D feature and covering a second portion of the fin under the second S/D feature; removing the first portion of the fin, resulting in a first trench; forming a first dielectric feature in the first trench; and removing the second portion of the fin to form a second trench. The first dielectric feature and the isolation structure form first and second sidewalls of the second trench respectively. The method includes laterally etching the second sidewalls, thereby expanding the second trench along the second direction and forming a via structure in the expanded second trench.

公开(公告)号：US11848368B2

公开(公告)日：2023-12-19

申请号：US17504206

申请日：2021-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/28061 ,  H01L21/28088 ,  H01L21/32051 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0665 ,  H01L2029/7858

Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.

公开(公告)号：US20230387266A1

公开(公告)日：2023-11-30

申请号：US18366370

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L29/7851 ,  H01L27/0924 ,  H01L29/0653 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823431

Abstract: A semiconductor structure includes a power rail; an isolation structure over the power rail; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature; one or more channel layers over the isolation structure and connecting the first and the second S/D features; a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail; and a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail. The first via structure has a first width in a first cross-section perpendicular to the first direction, the first dielectric feature has a second width in a second cross-section parallel to the first cross-section, and the first width is greater than the second width.

公开(公告)号：US20230386971A1

公开(公告)日：2023-11-30

申请号：US18149899

申请日：2023-01-04

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Chih-Hao Wang

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/76224 ,  H01L27/088

Abstract: Methods of forming through vias for providing connections between a front-side of a substrate and a backside of the substrate and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure on a substrate; a first isolation feature extending partially through the gate structure; a first conductive feature extending through the first isolation feature; and a second conductive feature extending partially through the gate structure, the second conductive feature being electrically coupled to the first conductive feature.

公开(公告)号：US11830769B2

公开(公告)日：2023-11-28

申请号：US17869337

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/76 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/7682 ,  H01L21/76 ,  H01L21/76834 ,  H01L23/5286 ,  H01L23/53295 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02172 ,  H01L21/02274 ,  H01L29/0673

Abstract: A semiconductor structure includes first and second source/drain (S/D) features, one or more semiconductor channel layers connecting the first and second S/D features, a gate structure engaging the one or more semiconductor channel layers, a metal wiring layer at a backside of the semiconductor structure, an S/D contact electrically connecting the first S/D feature to the metal wiring layer, and a seal layer between the metal wiring layer and the gate structure. The seal layer is spaced away from the gate structure by an air gap therebetween.

公开(公告)号：US20230369458A1

公开(公告)日：2023-11-16

申请号：US18355253

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/6656 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.