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公开(公告)号：US12075714B2
公开(公告)日：2024-08-27
申请号：US17818617
申请日：2022-08-09
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Matteo Impalà , Cécile Colette Solange Nail
CPC classification number: H10N70/882 , G11C13/003 , H10N70/826
Abstract: Methods, systems, and devices for random number generation based on threshold voltage randomness are described. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.
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公开(公告)号：US12033695B2
公开(公告)日：2024-07-09
申请号：US17740062
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Alessandro Sebastiani , Mattia Robustelli , Matteo Impalà
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092
Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.
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公开(公告)号：US11996141B2
公开(公告)日：2024-05-28
申请号：US17716740
申请日：2022-04-08
Applicant: Micron Technology, Inc.
Inventor： Mattia Robustelli , Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano
CPC classification number: G11C11/56 , G11C7/1051 , G11C7/1096
Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
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公开(公告)号：US11922056B2
公开(公告)日：2024-03-05
申请号：US17977046
申请日：2022-10-31
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Innocenzo Tortorelli
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673 , G06N3/08 , G11C11/54 , G11C13/004 , G11C13/0069 , G11C13/0004 , G11C2013/0047 , G11C2213/30 , H10N70/882
Abstract: An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.
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公开(公告)号：US20240029796A1
公开(公告)日：2024-01-25
申请号：US17868750
申请日：2022-07-19
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Mattia Robustelli , Alessandro Sebastiani , Matteo Impala' , Fabio Pellizzer
CPC classification number: G11C16/102 , G11C16/20 , G11C16/0425
Abstract: Systems, methods, and apparatuses are provided for unipolar programming of memory cells in a semiconductor device. A memory has a plurality of self-selecting memory cells and circuitry configured to program a self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a current pulse to the self-selecting memory cell. The current is a set pulse or a reset pulse. The set pulse and the reset pulse have a same polarity.
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Patent Agency Ranking
公开(公告)号：US20230386572A1
公开(公告)日：2023-11-30
申请号：US17752785
申请日：2022-05-24
Applicant: Micron Technology, Inc.
Inventor： Mattia Robustelli , Innocenzo Tortorelli
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C13/0069 , G11C13/0038 , G11C13/0004 , G11C13/003
Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes a memory array. The memory array has first tiles and second tiles. Each of the tiles includes memory cells. Wordlines are configured to select the memory cells in the first and second tiles. A controller programs the selected memory cells by applying a first voltage to a first wordline, and a second voltage to a second wordline. The first and second voltages are applied in a counter-phase manner. The second voltages boosted by charge sharing between the first and second wordlines.
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公开(公告)号：US20230360699A1
公开(公告)日：2023-11-09
申请号：US17740062
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Alessandro Sebastiani , Mattia Robustelli , Matteo Impalà
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C13/0097
Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.
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公开(公告)号：US20230360681A1
公开(公告)日：2023-11-09
申请号：US17740069
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Mattia Boniardi , Innocenzo Tortorelli
CPC classification number: G11C7/1039 , G11C7/106 , G11C7/1087 , G11C7/1093 , G11C7/1066 , G11C16/3404
Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.
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公开(公告)号：US11735276B2
公开(公告)日：2023-08-22
申请号：US17361194
申请日：2021-06-28
Applicant: Micron Technology, Inc.
Inventor： Alessandro Sebastiani , Innocenzo Tortorelli
CPC classification number: G11C16/30 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/3404
Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A method may include writing memory cells to an intermediate state based on receiving a write command. Writing the intermediate state may include applying a first pulse having a first polarity to the memory cell. The method may include isolating a first access line coupled with the memory cell from a voltage source based on applying the first pulse. The method may also include applying a second pulse to a second access line coupled with the memory cell based on isolating the first access line.
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公开(公告)号：US11615844B2
公开(公告)日：2023-03-28
申请号：US17443203
申请日：2021-07-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Innocenzo Tortorelli , Stephen Tang , Christina Papagianni
Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.
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