公开(公告)号：US20190035467A1

公开(公告)日：2019-01-31

申请号：US16149261

申请日：2018-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34

Abstract: Memory devices include a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line.

公开(公告)号：US20190013080A1

公开(公告)日：2019-01-10

申请号：US16130324

申请日：2018-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Aaron Yip

IPC: G11C16/28 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C16/34 ,  G11C7/02 ,  G11C16/10

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

公开(公告)号：US20190013077A1

公开(公告)日：2019-01-10

申请号：US16127469

申请日：2018-09-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of series-connected memory cells of the plurality of strings of series-connected memory cells may be selectively connected to a common data line through a corresponding respective select gate, a first set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a second set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.

公开(公告)号：US10170490B2

公开(公告)日：2019-01-01

申请号：US15450638

申请日：2017-03-06

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11526 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.

公开(公告)号：US20180308548A1

公开(公告)日：2018-10-25

申请号：US16021306

申请日：2018-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34

Abstract: Memory devices having selectively electrically connected data lines with no intervening memory cells.

公开(公告)号：US10102914B2

公开(公告)日：2018-10-16

申请号：US15673218

申请日：2017-08-09

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/12 ,  G11C16/26 ,  G11C16/10 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

Abstract: Embodiments are provided that include a method including providing a first voltage to a selected memory cell and providing a second voltage to the selected memory cell during an operation. The first voltage is greater in magnitude than the second voltage and the first voltage is applied for a shorter duration than the second voltage. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.

公开(公告)号：US20180151201A1

公开(公告)日：2018-05-31

申请号：US15878121

申请日：2018-01-23

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11524 ,  G11C16/26 ,  G11C16/10 ,  G11C7/12 ,  G11C5/02 ,  G11C7/22 ,  G11C16/08 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/12 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US20180145029A1

公开(公告)日：2018-05-24

申请号：US15875407

申请日：2018-01-19

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

公开(公告)号：US20180136845A1

公开(公告)日：2018-05-17

申请号：US15854622

申请日：2017-12-26

Applicant: Micron Technology, Inc.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/42 ,  G11C8/12 ,  G11C11/5642 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US09881686B2

公开(公告)日：2018-01-30

申请号：US15393719

申请日：2016-12-29

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.