公开(公告)号：US10762010B2

公开(公告)日：2020-09-01

申请号：US15808595

申请日：2017-11-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US10734064B1

公开(公告)日：2020-08-04

申请号：US15992100

申请日：2018-05-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G06F12/14 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4072 ,  G11C29/38 ,  G11C29/32 ,  G11C29/22 ,  G11C5/04

Abstract: A memory control component has control circuitry and a data interface, the data interface to be coupled, via a plurality of data signaling paths, to a respective plurality of memory dies disposed on a memory module. The control circuitry transmits to the memory module a first configuration value that specifies a memory die quantity N that is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value. Thereafter, the control circuitry transmits a memory read command to the memory module to enable, in accordance with the first configuration value, a quantity N of the memory dies to output read data and enables the data interface to receive the read data via a respective quantity N of the data signaling paths.

公开(公告)号：US10705912B2

公开(公告)日：2020-07-07

申请号：US15990078

申请日：2018-05-25

Applicant: Rambus Inc.

Inventor： Michael Miller ,  Stephen Magee ,  John Eric Linstadt

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

公开(公告)号：US20200176617A1

公开(公告)日：2020-06-04

申请号：US16673431

申请日：2019-11-04

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F13/372 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US20190259435A1

公开(公告)日：2019-08-22

申请号：US16344321

申请日：2017-10-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/00 ,  G11C14/00 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0895 ,  G11C5/04

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

公开(公告)号：US10386788B2

公开(公告)日：2019-08-20

申请号：US15342329

申请日：2016-11-03

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  David G. Stork ,  John Eric Linstadt

IPC: G03H1/04 ,  H04N5/369 ,  G03H1/00 ,  H01L27/146 ,  H04N5/225 ,  H04N5/232 ,  H04N5/33

Abstract: An infrared imaging system includes a phase grating overlying a two-dimensional array of thermally sensitive pixels. The phase grating comprises a two-dimensional array of identical subgratings that define a system of Cartesian coordinates. The subgrating and pixel arrays are sized and oriented such that the pixels are evenly distributed with respect to the row and column intersections of the subgratings. The location of each pixel thus maps to a unique location beneath a virtual archetypical subgrating.

公开(公告)号：US10360972B2

公开(公告)日：2019-07-23

申请号：US15552569

申请日：2016-02-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C5/02 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  G11C11/4096 ,  H01L25/18 ,  G11C7/10 ,  G11C8/12 ,  H01L23/00

Abstract: A memory system includes dynamic random-access memory (DRAM) component that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US20190115059A1

公开(公告)日：2019-04-18

申请号：US15555470

申请日：2016-03-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt

IPC: G11C11/00 ,  G11C7/12 ,  G11C7/10 ,  G06F3/06 ,  G06F11/10

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

公开(公告)号：US10223309B2

公开(公告)日：2019-03-05

申请号：US15533630

申请日：2015-10-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16 ,  G11C7/10 ,  G11C5/04

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US20180366181A1

公开(公告)日：2018-12-20

申请号：US16011539

申请日：2018-06-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G06F11/10 ,  G11C29/52 ,  G11C7/02 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.