公开(公告)号：US10121704B2

公开(公告)日：2018-11-06

申请号：US15861692

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8238 ,  H01L21/70 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure. The gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.

公开(公告)号：US10090203B2

公开(公告)日：2018-10-02

申请号：US15604675

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

公开(公告)号：US20180261589A1

公开(公告)日：2018-09-13

申请号：US15980759

申请日：2018-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuei-Chun Hung

IPC: H01L27/02 ,  H01L27/11582 ,  H01L21/3213

CPC classification number: H01L27/0207 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

公开(公告)号：US09978873B2

公开(公告)日：2018-05-22

申请号：US15834070

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: The present invention provides a method of fabricating a FinFET, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an STI disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the STI not covered by the gate structure are etched, until the STI is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.

公开(公告)号：US20180138180A1

公开(公告)日：2018-05-17

申请号：US15802472

申请日：2017-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/225 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/02129 ,  H01L21/0217 ,  H01L21/2256 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823892 ,  H01L27/0886 ,  H01L29/66803

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.

公开(公告)号：US20180097098A1

公开(公告)日：2018-04-05

申请号：US15834070

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: The present invention provides a method of fabricating a FinFET, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an STI disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the STI not covered by the gate structure are etched, until the STI is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.

公开(公告)号：US20180047635A1

公开(公告)日：2018-02-15

申请号：US15264590

申请日：2016-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.

公开(公告)号：US09806031B2

公开(公告)日：2017-10-31

申请号：US14692761

申请日：2015-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L23/544 ,  H01L21/66 ,  G03F7/20

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26

Abstract: A monitor method for process control in a semiconductor fabrication process is disclosed. A first alignment mark is formed in a layer on a substrate, and its position is measured and stored in a first measurement data. A fabrication process is then performed. Afterwards, another measurement is performed to measure the position of the first alignment mark and to generate a second measurement data. Finally, an offset value between the position of the first alignment mark in the first measurement data and those in the second measurement data is calculated.

公开(公告)号：US09711358B2

公开(公告)日：2017-07-18

申请号：US15399715

申请日：2017-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Te Chen ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Shin-Feng Su ,  Yu-Ting Hung ,  Meng-Lin Tsai

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/0275 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816

Abstract: A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.

公开(公告)号：US09660022B2

公开(公告)日：2017-05-23

申请号：US14830756

申请日：2015-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chia-Hsun Tseng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of fabricating a single diffusion break includes providing a fin with two gate structures crossing the fin and a middle dummy gate structure crossing the fin, wherein the middle dummy gate structure is sandwiched by the gate structures. Later, numerous spacers are formed and each spacer respectively surrounds the gate structures and the middle dummy gate structure. Then, the middle dummy gate structure, and part of the fin directly under the middle dummy gate structure are removed to form a recess. Finally, an isolating layer in the recess is formed to close an entrance of the recess so as to form a void embedded within the recess.