公开(公告)号：US20230317715A1

公开(公告)日：2023-10-05

申请号：US17732570

申请日：2022-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Chun-Hsien Lin ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/94 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L29/7851 ,  H01L29/66181 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/94

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

公开(公告)号：US11778922B2

公开(公告)日：2023-10-03

申请号：US17533003

申请日：2021-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L41/47 ,  H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

CPC classification number: H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

公开(公告)号：US11778830B2

公开(公告)日：2023-10-03

申请号：US17979789

申请日：2022-11-03

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang

IPC: H10B43/30 ,  H10B41/10 ,  H10B41/30 ,  H10B43/10

CPC classification number: H10B43/30 ,  H10B41/10 ,  H10B41/30 ,  H10B43/10

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

公开(公告)号：US11774392B1

公开(公告)日：2023-10-03

申请号：US17701689

申请日：2022-03-23

Applicant: United Microelectronics Corp.

Inventor： Tsong-Lin Shen ,  Tsung-Yu Yang

IPC: G01N27/24 ,  G01R31/28

CPC classification number: G01N27/24 ,  G01R31/2831

Abstract: A chip crack detection structure, including a substrate, a first chip crack detection ring, a second chip crack detection ring, and a seal ring, is provided. The first chip crack detection ring includes multiple first conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the first conductive layers is not in contact with any plug. The second chip crack detection ring surrounds the first chip crack detection ring. The second chip crack detection ring includes multiple second conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the second conductive layers is not in contact with any plug. The seal ring surrounds the second chip crack detection ring. The seal ring includes multiple third conductive layers stacked over the substrate and electrically connected to each other.

公开(公告)号：US20230309309A1

公开(公告)日：2023-09-28

申请号：US17722403

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H01L27/11568 ,  H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L29/4234 ,  H01L29/792 ,  H01L29/40117 ,  H01L29/66833

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

公开(公告)号：US11769833B2

公开(公告)日：2023-09-26

申请号：US17956840

申请日：2022-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L29/0657 ,  H01L29/6656 ,  H01L29/66553

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

公开(公告)号：US20230299160A1

公开(公告)日：2023-09-21

申请号：US18199967

申请日：2023-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  Xiaojuan Gao ,  CHI REN

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/66825 ,  H01L29/40114 ,  H01L29/7883

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

公开(公告)号：US11764261B2

公开(公告)日：2023-09-19

申请号：US17670528

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US20230290839A1

公开(公告)日：2023-09-14

申请号：US18199359

申请日：2023-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Ruey-Chyr Lee

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/0684

Abstract: A high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation layer and the mesa structure. The mesa structure includes a channel layer, a barrier layer on the channel layer, two opposite first edges extending along a first direction, and two opposite second edges extending along a second direction. The contact structure includes a body portion and a plurality of protruding portions. The body portion penetrates through the passivation layer. The protruding portions penetrate through the barrier layer and a portion of the channel layer. In a top view, the body portion overlaps the two opposite first edges of the mesa structure without overlapping the two opposite second edges of the mesa structure.

公开(公告)号：US11757016B2

公开(公告)日：2023-09-12

申请号：US17709385

申请日：2022-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L27/092 ,  H01L29/401

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.