公开(公告)号：US20230326983A1

公开(公告)日：2023-10-12

申请号：US18329126

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L21/28097 ,  H01L21/28158 ,  H01L21/823475

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

公开(公告)号：US20230282720A1

公开(公告)日：2023-09-07

申请号：US18305839

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.

公开(公告)号：US11749728B2

公开(公告)日：2023-09-05

申请号：US17401970

申请日：2021-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L27/088 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H01L29/41725 ,  H01L21/0228 ,  H01L21/28556 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/66545 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US11695073B2

公开(公告)日：2023-07-04

申请号：US17072367

申请日：2020-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L29/78 ,  G11C11/22 ,  H01L29/24 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L29/78391 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

公开(公告)号：US11670691B2

公开(公告)日：2023-06-06

申请号：US17504259

申请日：2021-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L29/41725 ,  H01L21/28097 ,  H01L21/28158 ,  H01L21/823475

Abstract: A device includes a substrate, a gate structure over the substrate, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer, wherein a bottom surface of the dielectric liner is spaced away from the silicide by a gap, and an S/D contact over the silicide and at least partially filling the gap.

公开(公告)号：US11653500B2

公开(公告)日：2023-05-16

申请号：US17125435

申请日：2020-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Chang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H01L27/11597 ,  H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L23/535 ,  H01L27/1159 ,  H01L29/66

CPC classification number: H01L27/11597 ,  G11C11/2255 ,  H01L23/535 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/6684 ,  H01L29/66787 ,  H01L29/78391

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

公开(公告)号：US11631698B2

公开(公告)日：2023-04-18

申请号：US17070536

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/11585 ,  H01L27/11578 ,  H01L27/11592 ,  H01L27/1159

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

公开(公告)号：US11621352B2

公开(公告)日：2023-04-04

申请号：US17201812

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L21/321 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51

Abstract: A method comprises forming a gate structure over a substrate; forming a gate helmet to cap the gate structure; forming a source/drain contact on the substrate; depositing a contact etch stop layer (CESL) over the gate helmet and the source/drain contacts, and an interlayer dielectric (ILD) layer over the CESL; performing a first etching process to form a gate contact opening extending through the ILD layer, the CESL and the gate helmet to the gate structure; forming a metal cap in the gate contact opening; with the metal cap in the gate contact opening, performing a second etching process to form a source/drain via opening extending through the ILD layer, the CESL to the source/drain contact; and after forming the source/drain via opening, forming a gate contact over the metal cap and a source/drain via over the source/drain contact.

公开(公告)号：US11616080B2

公开(公告)日：2023-03-28

申请号：US17033006

申请日：2020-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/24

Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

公开(公告)号：US11532518B2

公开(公告)日：2022-12-20

申请号：US17178762

申请日：2021-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/033 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/768

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.