公开(公告)号：US20240256846A1

公开(公告)日：2024-08-01

申请号：US18135664

申请日：2023-04-17

Applicant: Silicon Storage Technology, Inc

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G06N3/065

CPC classification number: G06N3/065

Abstract: Numerous examples are disclosed of multiplexors coupled to rows in a neural network array. In one example, a system comprises a neural network array of non-volatile memory cells comprising i rows, where i is a multiple of 2; j row registers, where j

公开(公告)号：US20240256146A1

公开(公告)日：2024-08-01

申请号：US18134928

申请日：2023-04-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Kha Nguyen ,  Stephen Trinh ,  Stanley Hong ,  Hien Pham

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Numerous examples are disclosed of systems and methods to implement redundancy. In one example, a system comprises an array of non-volatile memory cells; a redundant array of non-volatile memory cells; and an input block coupled to respective rows in the array and respective rows in the redundant array and comprising row tag registers and redundant row tag registers.

公开(公告)号：US20240171069A1

公开(公告)日：2024-05-23

申请号：US18109397

申请日：2023-02-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Nghia Nguyen ,  Hien Lai ,  Thoan Nguyen ,  Son Nguyen ,  Viet Nguyen

IPC: H02M3/07 ,  G11C5/14

CPC classification number: H02M3/076 ,  G11C5/145

Abstract: Examples of improved charge pumps are disclosed. In one example, a system comprises a first charge path comprising a first stage to boost an input voltage and a second stage to boost a voltage received from the first stage of the first charge path; and a second charge path comprising a first stage to boost an input voltage and a second stage to boost a voltage received from the first stage of the second charge path; wherein an output of the second stage of the first charge path is coupled to the first stage of the second charge path and an output of the second stage of the second charge path is coupled to the first stage of the first charge path.

公开(公告)号：US20240127890A1

公开(公告)日：2024-04-18

申请号：US18536147

申请日：2023-12-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  ANH LY ,  NHAN DO ,  MARK REITEN

IPC: G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.

公开(公告)号：US20240120009A1

公开(公告)日：2024-04-11

申请号：US18530832

申请日：2023-12-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  NHAN DO ,  Mark REITEN

IPC: G11C16/10 ,  G06F17/16 ,  G06N3/0442 ,  G06N3/063 ,  G11C11/54

CPC classification number: G11C16/10 ,  G06F17/16 ,  G06N3/0442 ,  G06N3/063 ,  G11C11/54 ,  G11C2216/04

Abstract: In one example, a method comprises applying a first programming pulse to a terminal of a selected non-volatile memory cell; and applying a second programming pulse to the terminal of the selected non-volatile memory cell, wherein a magnitude of a voltage the second programming pulse is equal to or lower than a magnitude of a voltage of the first programming pulse; wherein the selected non-volatile memory cell is programmed to a target value by the first programming pulse and the second programming pulse.

公开(公告)号：US20240112729A1

公开(公告)日：2024-04-04

申请号：US18076129

申请日：2022-12-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Stephen TRINH ,  Stanley HONG ,  Thuan VU ,  Anh LY ,  Fan LUO

IPC: G11C11/56 ,  G06N3/04 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G06N3/04 ,  G11C11/5671 ,  G11C16/10 ,  G11C2216/04

Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.

公开(公告)号：US20240105263A1

公开(公告)日：2024-03-28

申请号：US18536123

申请日：2023-12-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Thuan VU ,  Stanley HONG ,  Stephen TRINH ,  Anh LY ,  Nhan DO ,  Mark REITEN

IPC: G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.

公开(公告)号：US20240098991A1

公开(公告)日：2024-03-21

申请号：US18520526

申请日：2023-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Toan Le ,  Nghia Le ,  Hien Pham

IPC: H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

CPC classification number: H10B41/42 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

公开(公告)号：US11915747B2

公开(公告)日：2024-02-27

申请号：US17856839

申请日：2022-07-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G06N3/065

CPC classification number: G11C11/54 ,  G06N3/065 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C2216/04

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

公开(公告)号：US11893478B2

公开(公告)日：2024-02-06

申请号：US17367542

申请日：2021-07-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G06N3/065 ,  G06N3/04

CPC classification number: G06N3/065 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for programmable output blocks for use with a VMM array within an artificial neural network. In one embodiment, the gain of an output block can be configured by a configuration signal. In another embodiment, the resolution of an ADC in the output block can be configured by a configuration signal.