公开(公告)号：US20240393537A1

公开(公告)日：2024-11-28

申请号：US18788558

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiwei Song ,  Stefan Rusu ,  Chewn-Pu Jou ,  Huan-Neng Chen

IPC: G02B6/293 ,  G02B6/122 ,  G02B6/14 ,  H01S5/30

Abstract: A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.

公开(公告)号：US12154974B2

公开(公告)日：2024-11-26

申请号：US18521556

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

IPC: H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

公开(公告)号：US12154829B2

公开(公告)日：2024-11-26

申请号：US17070232

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping and to form multiple devices with different Vt. The method includes forming a gate dielectric layer on a fin structure, forming a buffer layer on the gate dielectric layer, and forming a dopant source layer including a dopant on the buffer layer. The gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. The method further includes doping a portion of the high-k dielectric layer adjacent to the interfacial layer with the dopant, removing the dopant source layer and the buffer layer, forming a dopant pulling layer on the gate dielectric layer, and tuning the dopant in the gate dielectric layer by the dopant pulling layer.

公开(公告)号：US12154784B2

公开(公告)日：2024-11-26

申请号：US17720033

申请日：2022-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Hung ,  Huan-Just Lin ,  Sheng-Liang Pan ,  Yungtzu Chen ,  Po-Chuan Wang ,  Guan-Xuan Chen

IPC: H01L21/02 ,  H01L21/8234

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

公开(公告)号：US12153339B2

公开(公告)日：2024-11-26

申请号：US17390603

申请日：2021-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/64 ,  B82Y30/00 ,  B82Y40/00 ,  G03F1/82 ,  G03F7/00 ,  H01L21/033

Abstract: A pellicle for protecting a photomask from contaminant particles is provided. The pellicle includes a pellicle membrane containing at least one porous film. The at least one porous film includes a network of a plurality of nanotubes. At least one nanotube of the plurality of nanotubes includes a core nanotube and a shell nanotube surrounding the core nanotube. The core nanotube includes a material different from the shell nanotube. The pellicle further includes a pellicle border attached to the pellicle membrane along a peripheral region of the pellicle membrane and a pellicle frame attached to the pellicle border.

公开(公告)号：US20240389462A1

公开(公告)日：2024-11-21

申请号：US18789481

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ting-Jung CHEN

IPC: H10N30/063 ,  H10N30/09 ,  H10N30/50 ,  H10N30/87

Abstract: A method for forming a MEMS device is provided. The method includes forming a stack of layers on a base piezoelectric layer. The stack of layers includes a base metal film over the base piezoelectric layer; a first piezoelectric film over the base metal film; and a first metal film having an opening therein over the first piezoelectric film. The method also includes forming a trench in the stack of layers, wherein the trench passes through the opening in the first metal film but does not expose the base metal film; after forming the trench, forming a spacer structure under the first metal film but spaced apart from the base metal film; after forming the spacer structure, deepening the trench to expose the base metal film; and forming a contact in the trench.

公开(公告)号：US20240387747A1

公开(公告)日：2024-11-21

申请号：US18788580

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chunchieh Wang ,  Yueh-Ching Pai

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region, a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region, a gate dielectric layer wrapping around each of the first and second sets of nanostructures, a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures, a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, and a fill layer on the second work function tuning layer.

公开(公告)号：US20240387711A1

公开(公告)日：2024-11-21

申请号：US18788347

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H Diaz ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/426 ,  H01L21/441 ,  H01L21/461 ,  H01L21/477 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

公开(公告)号：US20240387704A1

公开(公告)日：2024-11-21

申请号：US18785474

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Che-Hao Chang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.

公开(公告)号：US20240387683A1

公开(公告)日：2024-11-21

申请号：US18785381

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Chun Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, two source/drain (S/D) regions over the substrate, a channel region between the two S/D regions and including a semiconductor material, a deposited capacitor material (DCM) layer over the channel region a dielectric layer over the DCM layer and a metallic gate electrode layer over the dielectric layer.