公开(公告)号：US20220310849A1

公开(公告)日：2022-09-29

申请号：US17840186

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Juan ALZATE VINASCO

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/108 ,  H01L29/49

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US20220157984A1

公开(公告)日：2022-05-19

申请号：US17589831

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Tahir GHANI ,  Stephen CEA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

公开(公告)号：US20220102557A1

公开(公告)日：2022-03-31

申请号：US17549827

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

公开(公告)号：US20220037530A1

公开(公告)日：2022-02-03

申请号：US17497864

申请日：2021-10-08

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN ,  Cory C. BOMBERGER ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/161 ,  H01L27/088

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US20210296180A1

公开(公告)日：2021-09-23

申请号：US17336565

申请日：2021-06-02

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Willy RACHMADY ,  Anand S. MURTHY ,  Chandra S. MOHAPATRA ,  Tahir GHANI ,  Sean T. MA ,  Jack T. KAVALIEROS

IPC: H01L21/8234 ,  H01L21/02

Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.

公开(公告)号：US20210234022A1

公开(公告)日：2021-07-29

申请号：US17227165

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Tahir GHANI ,  Atul MADHAVAN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

公开(公告)号：US20210193807A1

公开(公告)日：2021-06-24

申请号：US16719281

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Tahir GHANI ,  Kalyan KOLLURU ,  Nathan JACK ,  Nicholas THOMSON ,  Ayan KAR ,  Benjamin ORR

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L25/18 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US20210193652A1

公开(公告)日：2021-06-24

申请号：US16719257

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Tahir GHANI ,  Kalyan KOLLURU ,  Nathan JACK ,  Nicholas THOMSON ,  Ayan KAR ,  Benjamin ORR

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US20210175233A1

公开(公告)日：2021-06-10

申请号：US17183214

申请日：2021-02-23

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20210134673A1

公开(公告)日：2021-05-06

申请号：US17147423

申请日：2021-01-12

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.