Elevationally-Elongated Conductive Structure Of Integrated Circuitry, Method Of Forming An Array Of Capacitors, Method Of Forming DRAM Circuitry, And Method Of Forming An Elevationally-Elongated Conductive Structure Of Integrated Circuitry

    公开(公告)号:US20200006472A1

    公开(公告)日:2020-01-02

    申请号:US16568504

    申请日:2019-09-12

    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias. Conductive material is formed directly above and directly against the conductive vias. The conductive material has an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section. The conductive material has a second sidewall that is not directly above the individual conductive vias. Covering material is formed directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias. The covering material comprises a composition different from that of at least some of the conductive material. Etching is conducted completely through at least some of the covering material that is directly above the individual upper surfaces to the conductive material directly there-below and etching is conducted into said conductive material. The covering material that is against the individual first sidewalls masks the individual first sidewalls from being etched during said etchings. Structure that may be independent of method is disclosed.

    Integrated assemblies which include carbon-doped oxide, and methods of forming integrated assemblies

    公开(公告)号:US10381352B1

    公开(公告)日:2019-08-13

    申请号:US15971210

    申请日:2018-05-04

    Abstract: Some embodiments include an integrated assembly having semiconductor material structures which each have a transistor channel region, and which are over metal-containing structures. Carbon-doped oxide is adjacent regions of each of the semiconductor material structures and sidewalls of the metal-containing structures. Some embodiments include an integrated assembly having pillars of semiconductor material. Each of the pillars has four sidewalls. Two of the four sidewalls of each pillar are gated sidewalls. The other two of the four sidewalls are non-gated sidewalls. Carbon-doped silicon dioxide is adjacent and directly against the non-gated sidewalls. Some embodiments include a method of forming an integrated assembly. Rails of semiconductor material are formed. A layer of carbon-doped silicon dioxide is formed adjacent top surfaces and sidewall surfaces of each of the rails. Trenches are formed which slice the semiconductor material of the rails into pillars. Wordlines are formed within the trenches and along the pillars.

    Apparatuses Having Body Connection Lines Coupled with Access Devices

    公开(公告)号:US20190181143A1

    公开(公告)日:2019-06-13

    申请号:US16279262

    申请日:2019-02-19

    Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

    Apparatuses Having Body Connection Lines Coupled with Access Devices

    公开(公告)号:US20180374855A1

    公开(公告)日:2018-12-27

    申请号:US15895928

    申请日:2018-02-13

    Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

    Methods of forming an elevationally extending conductor laterally between a pair of conductive lines

    公开(公告)号:US10134741B2

    公开(公告)日:2018-11-20

    申请号:US15652724

    申请日:2017-07-18

    Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

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