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公开(公告)号:US20200052113A1
公开(公告)日:2020-02-13
申请号:US16596423
申请日:2019-10-08
Applicant: Micron Technology, Inc.
Inventor: Sanh D. Tang , Hong Li , Erica L. Poelstra
IPC: H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/02 , H01L21/3105 , H01L29/10 , H01L23/528 , H01L29/06 , H01L21/308 , H01L21/311 , H01L27/108 , H01L27/24 , H01L21/762 , H01L23/49
Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.
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公开(公告)号:US20200006472A1
公开(公告)日:2020-01-02
申请号:US16568504
申请日:2019-09-12
Applicant: Micron Technology, Inc.
Inventor: Sanh D. Tang , Kuo-Chen Wang
IPC: H01L49/02 , H01L27/108 , H01L21/3213
Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias. Conductive material is formed directly above and directly against the conductive vias. The conductive material has an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section. The conductive material has a second sidewall that is not directly above the individual conductive vias. Covering material is formed directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias. The covering material comprises a composition different from that of at least some of the conductive material. Etching is conducted completely through at least some of the covering material that is directly above the individual upper surfaces to the conductive material directly there-below and etching is conducted into said conductive material. The covering material that is against the individual first sidewalls masks the individual first sidewalls from being etched during said etchings. Structure that may be independent of method is disclosed.
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233.
公开(公告)号:US10381352B1
公开(公告)日:2019-08-13
申请号:US15971210
申请日:2018-05-04
Applicant: Micron Technology, Inc.
Inventor: Sanh D. Tang , Silvia Borsari , Sau Ha Cheung
IPC: H01L27/108 , H01L21/02 , H01L23/528
Abstract: Some embodiments include an integrated assembly having semiconductor material structures which each have a transistor channel region, and which are over metal-containing structures. Carbon-doped oxide is adjacent regions of each of the semiconductor material structures and sidewalls of the metal-containing structures. Some embodiments include an integrated assembly having pillars of semiconductor material. Each of the pillars has four sidewalls. Two of the four sidewalls of each pillar are gated sidewalls. The other two of the four sidewalls are non-gated sidewalls. Carbon-doped silicon dioxide is adjacent and directly against the non-gated sidewalls. Some embodiments include a method of forming an integrated assembly. Rails of semiconductor material are formed. A layer of carbon-doped silicon dioxide is formed adjacent top surfaces and sidewall surfaces of each of the rails. Trenches are formed which slice the semiconductor material of the rails into pillars. Wordlines are formed within the trenches and along the pillars.
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234.
公开(公告)号:US20190198668A1
公开(公告)日:2019-06-27
申请号:US15976720
申请日:2018-05-10
Applicant: Micron Technology, Inc.
Inventor: Sanh D. Tang , Hong Li , Erica L. Poelstra
IPC: H01L29/78 , H01L21/762 , H01L21/8234 , H01L21/02 , H01L21/3105 , H01L29/10 , H01L23/528 , H01L29/06 , H01L21/308 , H01L21/311 , H01L27/108 , H01L27/24 , H01L29/66
Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.
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公开(公告)号:US20190181143A1
公开(公告)日:2019-06-13
申请号:US16279262
申请日:2019-02-19
Applicant: Micron Technology, Inc.
Inventor: Deepak Chandra Pandey , Haitao Liu , Chandra Mouli , Sanh D. Tang
IPC: H01L27/108 , H01L29/78
Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.
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公开(公告)号:US20190051653A1
公开(公告)日:2019-02-14
申请号:US16161381
申请日:2018-10-16
Applicant: Micron Technology, Inc.
Inventor: Sanh D. Tang , Kamal M. Karda , Wolfgang Mueller , Sourabh Dhir , Robert Kerr , Sangmin Hwang , Haitao Liu
IPC: H01L27/108 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/762 , H01L23/528
Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.
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公开(公告)号:US20180374855A1
公开(公告)日:2018-12-27
申请号:US15895928
申请日:2018-02-13
Applicant: Micron Technology, Inc.
Inventor: Deepak Chandra Pandey , Haitao Liu , Chandra Mouli , Sanh D. Tang
IPC: H01L27/108 , H01L29/78
Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.
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238.
公开(公告)号:US10134741B2
公开(公告)日:2018-11-20
申请号:US15652724
申请日:2017-07-18
Applicant: Micron Technology, Inc.
Inventor: Guangjun Yang , Russell A. Benson , Brent Gilgen , Alex J. Schrinsky , Sanh D. Tang , Si-Woo Lee
IPC: H01L21/768 , H01L27/108
Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.
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公开(公告)号:US10090324B2
公开(公告)日:2018-10-02
申请号:US15722580
申请日:2017-10-02
Applicant: Micron Technology, Inc.
Inventor: Sanh D. Tang , John K. Zahurak
IPC: H01L27/11582 , H01L23/528 , H01L27/06 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/24 , H01L29/66 , H01L29/788 , H01L29/792 , H01L21/768 , H01L21/28 , H01L27/11548 , H01L27/11575 , G11C13/00 , G11C16/10 , G11C16/14 , G11C16/26 , H01L27/11519 , H01L27/11565 , H01L45/00
Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
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公开(公告)号:US20180175059A1
公开(公告)日:2018-06-21
申请号:US15900188
申请日:2018-02-20
Applicant: Micron Technology, Inc.
Inventor: Sanh D. Tang , Roger W. Lindsay , Krishna K. Parat
IPC: H01L27/11582 , H01L27/1157 , H01L27/11524 , H01L45/00
CPC classification number: H01L23/52 , G11C13/0007 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75 , H01L23/528 , H01L27/10 , H01L27/101 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/249 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.
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