公开(公告)号：US20160196854A1

公开(公告)日：2016-07-07

申请号：US15070145

申请日：2016-03-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C5/14 ,  G06F1/206 ,  G06F1/3203 ,  G11C5/148 ,  G11C7/00 ,  H01L27/1203 ,  H01L29/786

Abstract: To provide a semiconductor device including a plurality of circuit blocks each of which is capable of performing power gating by setting off periods appropriate to temperatures of the respective circuit blocks. Specifically, the semiconductor device includes an arithmetic circuit, a memory circuit configured to hold data obtained by the arithmetic circuit, a power supply control switch configured to control supply of the power supply voltage to the arithmetic circuit, a temperature detection circuit configured to detect the temperature of the memory circuit and to estimate overhead from the temperature, and a controller configured to set a period during which supply of the power supply voltage is stopped in the case where a power consumption of the arithmetic circuit during the period is larger than the overhead period and to control the power supply control switch.

公开(公告)号：US20160195584A1

公开(公告)日：2016-07-07

申请号：US15067382

申请日：2016-03-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Jun KOYAMA

IPC: G01R31/36

CPC classification number: G01R31/3833 ,  G01R1/203 ,  G01R19/25 ,  G01R31/364 ,  G01R31/3832

Abstract: A coulomb counter is provided. In the coulomb counter, a current generated on charge or discharge of a secondary battery is converted into a voltage by a resistor, and the voltage is amplified by an amplifier circuit. The voltage amplified by the amplifier circuit is converted into a current by a voltage-current converter circuit, and the current is input to a cumulative addition circuit. The cumulative addition circuit charges a capacitor with the current input from the voltage-current converter circuit and generates a signal corresponding to a voltage generated across the capacitor. One terminal of the capacitor is connected to an output of the voltage-current converter circuit through a switch, and the other terminal of the capacitor is supplied with a constant potential. By on/off of the switch, supply of electric charge to the capacitor and storage of the electric charge can be controlled.

Abstract translation: 提供库仑计数器。 在库仑计数器中，二次电池充电或放电时产生的电流由电阻器转换成电压，并通过放大电路放大电压。 由放大器电路放大的电压由电压 - 电流转换器电路转换为电流，并且电流被输入到累积加法电路。 累积加法电路使电容器与来自电压 - 电流转换器电路的电流输入充电，并产生对应于电容器两端产生的电压的信号。 电容器的一个端子通过开关连接到电压 - 电流转换器电路的输出，并且电容器的另一个端子被提供恒定电位。 通过开/关开关，可以控制电容器的电荷供应和电荷的储存。

公开(公告)号：US20160140921A1

公开(公告)日：2016-05-19

申请号：US15007999

申请日：2016-01-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: G09G3/36

CPC classification number: G09G3/3618 ,  G02F1/1345 ,  G06F3/0416 ,  G06F3/0421 ,  G06F3/044 ,  G09G3/3648 ,  G09G3/3655 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2310/04 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0219 ,  G09G2320/10 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2340/16 ,  G09G2354/00

Abstract: The liquid crystal display device includes a first substrate provided with a terminal portion, a switching transistor, a driver circuit portion, and a pixel circuit portion including a pixel transistor and a plurality of pixels, a second substrate provided with a common electrode electrically connected to the terminal portion through the switching transistor, and liquid crystal between a pixel electrode and the common electrode. In a period during which a still image is switched to a moving image, the following steps are sequentially performed: a first step of supplying the common potential to the common electrode; a second step of supplying a power supply voltage to the driver circuit portion; a third step of supplying a clock signal to the driver circuit portion; and a fourth step of supplying a start pulse signal to the driver circuit portion.

公开(公告)号：US20160064570A1

公开(公告)日：2016-03-03

申请号：US14936305

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/02

CPC classification number: H01L29/7869 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/1225 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

Abstract translation: 逻辑电路包括具有使用氧化物半导体形成的沟道形成区域的薄膜晶体管，以及通过关闭薄膜晶体管而使端子中的一个成为浮置状态的电容器。 氧化物半导体的氢浓度为5×1019（原子/ cm3）以下，因此在不产生电场的状态下基本上用作绝缘体。 因此，可以减小薄膜晶体管的截止电流，从而通过薄膜晶体管抑制存储在电容器中的电荷的泄漏。 因此，可以防止逻辑电路的故障。 此外，可以通过减小薄膜晶体管的截止电流来降低在逻辑电路中流动的过量的电流，导致逻辑电路的低功耗。

公开(公告)号：US20160049520A1

公开(公告)日：2016-02-18

申请号：US14924857

申请日：2015-10-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masahiro TAKAHASHI ,  Hideyuki KISHIDA ,  Akiharu MIYANAGA ,  Junpei SUGAO ,  Hideki UOCHI ,  Yasuo NAKAMURA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/324 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76838 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

Abstract translation: 通过使用包含Cu的导电层作为长引线，可以抑制布线电阻的增加。 此外，包括Cu的导电层以与形成TFT的沟道区域的氧化物半导体层不重叠并被包括氮化硅的绝缘层包围的方式设置，由此Cu的扩散可以 防止 因此，可以制造高度可靠的半导体器件。 具体地说，作为半导体装置的一个实施方式的显示装置，即使在尺寸或定义增加的情况下也能够具有高的显示质量，并且稳定地工作。

公开(公告)号：US20150364477A1

公开(公告)日：2015-12-17

申请号：US14837177

申请日：2015-08-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/115 ,  H01L29/24 ,  H01L29/78 ,  H01L49/02 ,  H01L23/528 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L21/28518 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

Abstract translation: 第一晶体管，包括沟道形成区域，第一栅极绝缘层，第一栅极电极和第一源极电极以及第一漏极电极; 第二晶体管，包括氧化物半导体层，第二源极和第二漏极，第二栅极绝缘层和第二栅电极; 以及包括第二源电极和第二漏极之一的电容器，第二栅极绝缘层和设置成与第二栅极绝缘层上的第二源电极和第二漏电极之一重叠的电极。 第一栅极电极和第二源极电极和第二漏极电极中的一个彼此电连接。

公开(公告)号：US20150340539A1

公开(公告)日：2015-11-26

申请号：US14712292

申请日：2015-05-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA

IPC: H01L31/113 ,  H01L31/0224 ,  H01L31/032

CPC classification number: H01L31/1136 ,  G01J1/429 ,  H01L31/022408 ,  H01L31/032

Abstract: An ultraviolet light sensor (UV sensor) with low costs is provided. As a UV sensor element, an oxide semiconductor transistor including a drain electrode with a comb-like shape is used, so that the length of a border between the drain electrode and a channel region is greater than the length of a border between a source electrode and the channel region. As a result, the off-state current of the oxide semiconductor transistor can be increased without a significant increase in the gate width, improving the sensitivity of the UV sensor. In addition, a reduced area in the element is achieved to reduce costs of the UV sensor.

Abstract translation: 提供低成本的紫外线传感器（UV传感器）。 作为UV传感器元件，使用包括具有梳状形状的漏电极的氧化物半导体晶体管，使得漏电极和沟道区之间的边界的长度大于源电极 和通道区域。 结果，可以增加氧化物半导体晶体管的截止电流，而不会显着增加栅极宽度，从而提高UV传感器的灵敏度。 此外，实现元件的减小的面积以降低UV传感器的成本。

公开(公告)号：US20150325596A1

公开(公告)日：2015-11-12

申请号：US14804478

申请日：2015-07-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/12 ,  H01L27/115 ,  H01L29/16 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L27/1052 ,  G11C11/405 ,  G11C16/0433 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11803 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7833 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Abstract translation: 目的是提供具有新颖结构的半导体器件。 半导体器件包括第一布线; 第二布线 第三线; 第四布线 具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。 第一晶体管设置在包括半导体材料的衬底中。 第二晶体管包括氧化物半导体层。

公开(公告)号：US20150255141A1

公开(公告)日：2015-09-10

申请号：US14717071

申请日：2015-05-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: G11C11/407

CPC classification number: G11C11/407 ,  G11C5/025 ,  G11C8/08 ,  G11C11/404 ,  G11C11/4097

Abstract: In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured.

Abstract translation: 在存储装置中，确保了保持数据的期间的每单位面积的存储容量。 存储器件包括设置在衬底上的驱动器电路和设置在驱动器电路上并由驱动器电路驱动的多个存储单元阵列。 多个存储单元阵列中的每一个包括多个存储单元。 多个存储单元中的每一个包括第一晶体管，其包括与氧化物半导体层重叠的第一栅电极，以及包括源电极或漏电极，第一栅绝缘层和导电层的电容器。 堆叠多个存储单元阵列以重叠。 因此，在存储装置中，确保了保持数据的期间的每单位面积的存储容量。

公开(公告)号：US20150248857A1

公开(公告)日：2015-09-03

申请号：US14709880

申请日：2015-05-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: G09G3/30 ,  G09G5/18

CPC classification number: G09G3/30 ,  G09G3/3233 ,  G09G5/18 ,  G09G2300/0861

Abstract: A method for driving a light-emitting device comprises steps of: supplying a first potential to a drain of a transistor and a second potential being lower than the first potential to a cathode of a light-emitting element; supplying a third potential which is lower than a potential obtained by adding the threshold voltage of the transistor, the threshold voltage of the light-emitting element, and the second potential to a gate electrode of the transistor, and a fourth potential being lower than a potential obtained by subtracting the threshold voltage of the transistor from the third potential to the source of the transistor; stopping supply of the fourth potential to the source of the transistor; and supplying a potential of an image signal to the gate electrode of the transistor.

Abstract translation: 一种用于驱动发光器件的方法，包括以下步骤：向晶体管的漏极提供第一电位，将低于第一电位的第二电位提供给发光元件的阴极; 提供低于通过将晶体管的阈值电压，发光元件的阈值电压和第二电位加到晶体管的栅电极而获得的电位的第三电位，并且第四电位低于 通过从晶体管的第三电位减去晶体管的阈值电压而获得的电位; 停止向晶体管的源极供应第四电位; 以及向晶体管的栅电极提供图像信号的电位。