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    Split-Gate Flash Memory Cell With Improved Scaling Using Enhanced Lateral Control Gate To Floating Gate Coupling
    232.
    发明申请
    Split-Gate Flash Memory Cell With Improved Scaling Using Enhanced Lateral Control Gate To Floating Gate Coupling 审中-公开
    使用增强型横向控制门到浮动栅极耦合的改进的缩放分离栅极闪存单元

    公开(公告)号：US20160043095A1

    公开(公告)日：2016-02-11

    申请号：US14790540

    申请日：2015-07-02

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Chien-Sheng Su ,  Nhan Do

    IPC: H01L27/115 ,  H01L29/66

    CPC classification number: H01L27/11521 ,  H01L21/823425 ,  H01L21/823475 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

    Abstract translation: 非易失性存储单元包括在第二导电类型的衬底中的第一导电类型的第一和第二间隔开的区域的半导体衬底，以及衬底中的沟道区。 浮动栅极具有垂直设置在沟道区域的第一部分上的第一部分和垂直设置在第一区域上的第二部分。 浮动门包括倾斜的上表面，其以一个或多个尖锐边缘终止。 擦除栅极垂直设置在浮动栅极上，其中一个或多个尖锐边缘面向擦除栅极。 控制门具有横向邻近浮动栅极设置的第一部分，并且垂直地设置在第一区域上。 选择栅极具有垂直设置在沟道区域的第二部分上并且横向邻近浮置栅极的第一部分。

    Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same
    234.
    发明申请
    Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same 审中-公开
    具有绝缘体硅基板的嵌入式存储器件及其制造方法

    公开(公告)号：US20150263040A1

    公开(公告)日：2015-09-17

    申请号：US14216553

    申请日：2014-03-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do

    IPC: H01L27/12 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L29/78

    CPC classification number: H01L27/1203 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7841 ,  H01L29/7881

    Abstract: A semiconductor device having a silicon substrate with a first area including a buried insulation layer with silicon over and under the insulation layer and a second area in which the substrate lacks buried insulation disposed under any silicon. Logic devices are formed in the first area having spaced apart source and drain regions formed in the silicon that is over the insulation layer, and a conductive gate formed over and insulated from a portion of the silicon that is over the insulation layer and between the source and drain regions. Memory cells are formed in the second area that include spaced apart second source and second drain regions formed in the substrate and defining a channel region therebetween, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region.

    Abstract translation: 一种具有硅衬底的半导体器件，其具有第一区域，该第一区域包括在绝缘层之上和之下的具有硅的掩埋绝缘层，以及第二区域，其中衬底缺少设置在任何硅下的掩埋绝缘体。 逻辑器件形成在第一区域中，其中形成在绝缘层之上的硅中具有间隔开的源极和漏极区域，以及形成在绝缘层之上和源极之间的硅的一部分上并与其绝缘的导电栅极 和漏区。 存储单元形成在第二区域中，该第二区域包括形成在基板中的间隔开的第二源极和第二漏极区域，并且在其间限定沟道区域;布置在沟道区域的第一部分之上并与沟道区域的第一部分绝缘的浮置栅极;以及选择栅极 并且与沟道区域的第二部分绝缘。

    Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same
    235.
    发明申请
    Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same 审中-公开
    具有自对准浮动和擦除门的非易失性存储单元及其制造方法

    公开(公告)号：US20150179749A1

    公开(公告)日：2015-06-25

    申请号：US14133821

    申请日：2013-12-19

    Applicant: Silicon Storage Technology, Inc

    Inventor： Bomy Chen ,  Chien-Sheng Su ,  Nhan Do

    IPC: H01L29/423 ,  H01L29/66 ,  G11C16/10 ,  H01L29/788 ,  H01L27/115

    CPC classification number: H01L29/42328 ,  G11C16/0408 ,  G11C16/10 ,  H01L21/28238 ,  H01L27/11517 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

    Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. Any portion of the trench between the pair of floating gates is free of electrically conductive elements except for a lower portion of the erase gate.

    Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘，以控制其导电性。 擦除栅极至少部分地设置在浮栅上并与浮栅绝缘。 一对浮动栅极之间的沟槽的任何部分除了擦除栅极的下部以外没有导电元件。

    Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same
    236.
    发明申请
    Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same 有权
    具有自对准浮动和擦除门的非易失性存储单元及其制造方法

    公开(公告)号：US20140307511A1

    公开(公告)日：2014-10-16

    申请号：US14252929

    申请日：2014-04-15

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Jinho Kim ,  Xian Liu

    IPC: H01L27/115 ,  G11C16/12 ,  G11C16/14 ,  H01L29/66

    CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

    Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.

    Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘，以控制其导电性。 擦除栅极至少部分地布置在浮栅上并与浮栅绝缘。 导电耦合栅极设置在沟槽中，与浮动栅极相邻并与其隔离，并且与源极区域隔离并且绝缘。

    Non-volatile Memory Cell Having A Trapping Charge Layer In A Trench And An Array And A Method Of Manufacturing Therefor
    237.
    发明申请
    Non-volatile Memory Cell Having A Trapping Charge Layer In A Trench And An Array And A Method Of Manufacturing Therefor 有权
    在沟槽和阵列中具有捕获电荷层的非易失性存储单元及其制造方法

    公开(公告)号：US20140264530A1

    公开(公告)日：2014-09-18

    申请号：US13829111

    申请日：2013-03-14

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do

    IPC: H01L29/792 ,  H01L29/66 ,  H01L27/105

    CPC classification number: H01L29/66833 ,  H01L21/0217 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7926

    Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

    Abstract translation: 通过在衬底表面形成沟槽形成的存储单元。 第一和第二间隔开的区域形成在衬底中，其间具有通道区域。 第一区域形成在沟槽下方。 沟道区域包括沿着沟槽的侧壁延伸的第一部分和沿衬底的表面延伸的第二部分。 沟槽中的电荷捕获层与沟道区的第一部分相邻并与其绝缘，用于控制沟道区第一部分的导通。 沟槽中的导电栅极与电荷俘获层相邻并且与第一区绝缘，并与电荷捕获层电容耦合。 导电控制栅极设置在沟道区域的第二部分上并与沟道区域的第二部分绝缘，用于控制其导通。

    Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate
    238.
    发明申请
    Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate 有权
    使用耦合栅极操作分离栅极闪存单元的方法

    公开(公告)号：US20140198578A1

    公开(公告)日：2014-07-17

    申请号：US14216776

    申请日：2014-03-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'mani

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

    Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

    Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域的第一和第二区域，设置在所述沟道区域和所述第一区域上方的浮置栅极，设置在所述沟道区域上并横向邻近所述第二区域的方法 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

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