公开(公告)号：US11797455B2

公开(公告)日：2023-10-24

申请号：US16600897

申请日：2019-10-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jieming Yin ,  Subhash Sethumurugan ,  Yasuko Eckert

IPC: G06F12/12 ,  G06F12/0891 ,  G06F12/0855 ,  G06F12/126 ,  G06F12/0897 ,  G06F12/0871

CPC classification number: G06F12/0891 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0897 ,  G06F12/126

Abstract: A cache of a processor includes a cache controller to implement a cache management policy for the insertion and replacement of cache lines of the cache. The cache management policy assigns replacement priority levels to each cache line of at least a subset of cache lines in a region of the cache based on a comparison of a number of accesses to a cache set having a way that stores a cache line since the cache line was last accessed to a reuse distance determined for the region of the cache, wherein the reuse distance represents an average number of accesses to a given cache set of the region between accesses to any given cache line of the cache set.

公开(公告)号：US11790590B2

公开(公告)日：2023-10-17

申请号：US17218421

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind N. Nemlekar ,  Maxim V. Kazakov ,  Prerit Dak

IPC: G06T15/00 ,  G06F9/54 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06F9/545 ,  G06T15/80

Abstract: Techniques for executing computing work by a plurality of chiplets are provided. The techniques include assigning workgroups of a kernel dispatch packet to the chiplets; by each chiplet, executing the workgroups assigned to that chiplet; for each chiplet, upon completion of all workgroups assigned to that chiplet for the kernel dispatch packet, notifying the other chiplets of such completion; and upon completion of all workgroups of the kernel dispatch packet, notifying a client of such completion and proceeding to a subsequent kernel dispatch packet.

公开(公告)号：US11789734B2

公开(公告)日：2023-10-17

申请号：US16537460

申请日：2019-08-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Anupama Rajesh Rasale

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/3887

Abstract: A computing system includes a processing unit and a memory storing instructions that, when executed by the processor, cause the processor to receive program source code in a compiler, identify in the program source code a set of operations for vectorizing, where each operation in the set of operations specifies a set of one or more operands, in response to identifying the set of operations, vectorize the set of operations by, based on the number of operations in the set of operations and a total number of lanes in a first vector register, generating a mask indicating a first unmasked lane and a first masked lane in the first vector register, based on the mask, generating a set of one or more instructions for loading into the first unmasked lane a first operand of a first operation of the set of operations, and loading the first operand into the first masked lane.

公开(公告)号：US20230324967A1

公开(公告)日：2023-10-12

申请号：US17704862

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Amitabh Mehra ,  Grant Evan Ley ,  Anil Harwani ,  Joshua Taylor Knight

IPC: G06F1/20

CPC classification number: G06F1/206

Abstract: Package lids with carveouts configured to expose lights directly connected to an internal component of a processor are described. Lid carveouts are configured to precisely align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device via a press fit connection, while maintaining visibility of lights directly connected to processor internal components when the cooling device is connected. Lid carveouts are further configured to expose one or more connectors disposed on a processor surface that supports its internal component. When contacted by corresponding connectors of an auxiliary device, such as a light not integrated into a processor package or a cooling device, the lid carveouts enable direct connections between the package’s internal components and the auxiliary device.

公开(公告)号：US11782838B2

公开(公告)日：2023-10-10

申请号：US17219769

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Anirudh R. Acharya ,  Alexander Fuad Ashkar

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/10 ,  G06F12/0875

CPC classification number: G06F12/0862 ,  G06F12/0875 ,  G06F12/10 ,  G06F2212/6024

Abstract: Techniques for prefetching are provided. The techniques include receiving a first prefetch command; in response to determining that a history buffer indicates that first information associated with the first prefetch command has not already been prefetched, prefetching the first information into a memory; receiving a second prefetch command; and in response to determining that the history buffer indicates that second information associated with the second prefetch command has already been prefetched, avoiding prefetching the second information into the memory.

公开(公告)号：US11782640B2

公开(公告)日：2023-10-10

申请号：US17218703

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response elevates at least one of the priority and the age of a decoded command of the first type that accesses the first memory region already stored in the command queue.

公开(公告)号：US20230315468A1

公开(公告)日：2023-10-05

申请号：US17708318

申请日：2022-03-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ANTHONY JARVIS ,  THOMAS CLOUQUEUR ,  QIAN MA

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058

Abstract: Enforcing consistency across redundant tagged geometric (TAGE) branch histories, including: determining, by a TAGE branch predictor, whether a predefined interval has occurred; and storing, in a retirement branch history, in response to the predefined interval occurring, a copy of a global branch history.

公开(公告)号：US20230305981A1

公开(公告)日：2023-09-28

申请号：US18204604

申请日：2023-06-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. SALEH ,  Ruijin WU

IPC: G06F13/40 ,  G06T1/20 ,  G06F12/0815

CPC classification number: G06F13/4027 ,  G06T1/20 ,  G06F12/0815 ,  G06F2212/1032

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

公开(公告)号：US11768771B2

公开(公告)日：2023-09-26

申请号：US17547148

申请日：2021-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： John M. King ,  Gregory W. Smaus

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0844 ,  G06F12/0877 ,  G06F9/52

CPC classification number: G06F12/0844 ,  G06F9/522 ,  G06F12/0815 ,  G06F12/0877 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1032

Abstract: The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.

公开(公告)号：US11768664B2

公开(公告)日：2023-09-26

申请号：US16591031

申请日：2019-10-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Bin He ,  Michael Mantor ,  Jiasheng Chen

IPC: G06F7/57 ,  G06F7/544 ,  G06F9/38 ,  G06F7/483

CPC classification number: G06F7/57 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/3818 ,  G06F2207/3824

Abstract: A graphics processing unit (GPU) implements operations, with associated op codes, to perform mixed precision mathematical operations. The GPU includes an arithmetic logic unit (ALU) with different execution paths, wherein each execution path executes a different mixed precision operation. By implementing mixed precision operations at the ALU in response to designate op codes that delineate the operations, the GPU efficiently increases the precision of specified mathematical operations while reducing execution overhead.