公开(公告)号：US09202919B1

公开(公告)日：2015-12-01

申请号：US14447685

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

Abstract: Techniques and structures for shaping the source and drain junction profiles of a finFET are described. A fin may be partially recessed at the source and drain regions of the finFET. The partially recessed fin may be further recessed laterally and vertically, such that the laterally recessed portion extends under at least a portion of the finFET's gate structure. Source and drain regions of the finFET may be formed by growing a buffer layer on the etched surfaces of the fin and/or growing a source and drain layer at the source and drain regions of the fin. The lateral recess can improve channel-length uniformity along the height of the fin.

Abstract translation: 描述了用于成形finFET的源极和漏极结线廓的技术和结构。 翅片可以部分地凹陷在finFET的源极和漏极区域。 部分凹入的翅片可以进一步侧向和垂直地凹入，使得横向凹入部分在finFET的栅极结构的至少一部分下方延伸。 可以通过在鳍的蚀刻表面上生长缓冲层和/或在鳍的源极和漏极区生长源极和漏极层来形成鳍FET的源区和漏极区。 横向凹槽可以改善沿翅片高度的通道长度均匀性。

公开(公告)号：US20150333155A1

公开(公告)日：2015-11-19

申请号：US14281021

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  RUILONG XIE ,  XIUYU CAI ,  CHUN-CHEN YEH ,  KEJIA WANG

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

Abstract translation: 制造半导体器件的方法可以包括：形成第一和第二间隔开的半导体有源区域，其间具有绝缘区域，形成在第一和第二间隔开的半导体有源区域之间并在绝缘区域上延伸的至少一个牺牲栅极线，以及形成 在所述至少一个牺牲栅极线的相对侧上的侧壁间隔物。 该方法还可以包括去除侧壁间隔物内的至少一个牺牲栅极线的部分，并且在绝缘区域的上方限定限定至少一个栅极端部凹部的部分，用电介质材料填充至少一个栅极端部凹部，并且形成相应的 替代栅极代替在第一和第二间隔开的半导体有源区之上的至少一个牺牲栅极线的部分。

公开(公告)号：US20150323944A1

公开(公告)日：2015-11-12

申请号：US14270677

申请日：2014-05-06

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.R.L.

Inventor： Tom Youssef ,  Alessandro Gasparini ,  Yamu Hu ,  Naren K. Sahoo ,  Anthony Junior Casillan

IPC: G05F1/10

CPC classification number: G05F1/561 ,  G05F1/10

Abstract: A modulated digital input signal is passed through a conditioning circuit to generate a first input signal. An error amplifier circuit receives the first input signal and a second input signal, and controls the operation of a MOS transistor to generate an output signal that is current modulated. The output signal is sensed to generate a feedback signal. A switching circuit selectively applies the feedback signal as the second input signal in response to a transition of the modulated digital input signal from a first logic state to a second logic state. The switching circuit alternatively selectively applies a fixed reference signal as the second input signal to the error amplifier in response to a transition of the modulated digital input signal from the second logic state to the first logic state.

Abstract translation: 调制数字输入信号通过调理电路以产生第一输入信号。 误差放大器电路接收第一输入信号和第二输入信号，并且控制MOS晶体管的操作以产生电流调制的输出信号。 感测输出信号以产生反馈信号。 响应于调制的数字输入信号从第一逻辑状态到第二逻辑状态的转变，开关电路选择性地将反馈信号作为第二输入信号施加。 响应于调制的数字输入信号从第二逻辑状态到第一逻辑状态的转变，开关电路交替地选择性地将固定参考信号作为第二输入信号施加到误差放大器。

公开(公告)号：US20150287648A1

公开(公告)日：2015-10-08

申请号：US14583842

申请日：2014-12-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/8238 ,  H01L21/308 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/7849

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

Abstract translation: 半导体衬底包括沿着第一轴线延伸以限定宽度的体基板层和垂直于第一轴线的第二轴线以限定高度。 多个异质半导体鳍片包括形成在本体衬底层的第一区域上的外延材料。 在与第一区域不同的本体衬底层的第二区域上形成多个非异质半导体鳍片。 非异质半导体散热片从本体衬底层一体地形成，使得非异质半导体鳍片的材料与外延材料不同。

公开(公告)号：US20150270398A1

公开(公告)日：2015-09-24

申请号：US14223373

申请日：2014-03-24

Applicant: STMicroelectronics, Inc. ,  Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/308 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L21/28194 ,  H01L21/3085 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first epi semiconductor material and a second epi semiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity.

Abstract translation: 所公开的一种方法包括形成由半导体材料，第一外延半导体材料和第二外延半导体材料构成的鳍状结构，在鳍状结构之上形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物 执行至少一个蚀刻工艺以去除位于侧壁间隔件外侧的翅片结构的部分，从而在该装置的源极/漏极区域中限定翅片空腔并且暴露位于该侧壁间隔之下的翅片结构的边缘 并且执行外延沉积工艺以在位于侧壁间隔件下方和翅片腔内的翅片结构的暴露边缘上形成外延蚀刻停止层。

公开(公告)号：US20150255605A1

公开(公告)日：2015-09-10

申请号：US14201555

申请日：2014-03-07

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Ali Khakifirooz ,  Pierre Morin ,  Sanjay C. Mehta

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET.

Abstract translation: 描述了在全绝缘finFET中增加应变的方法和结构。 finFET结构可以形成在绝缘层上，并且包括绝缘的源极，沟道和漏极区域。 在制造期间，源区和漏区可以形成为悬挂结构。 应变诱导材料可以在四个相邻侧面上的源极和漏极区域周围形成，以便对finFET的沟道区域施加应力。

公开(公告)号：US20150228777A1

公开(公告)日：2015-08-13

申请号：US14175308

申请日：2014-02-07

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78684 ,  H01L29/78696

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Abstract translation: 具有部分凹陷栅极的晶体管被​​构造在具有掩埋氧化物层（BOX）的例如FD-SOI和UTBB器件的绝缘体上硅（SOI）半导体晶片上。 外延生长的沟道区域放宽了掺杂源极和漏极配置图的限制。 部分凹入的栅极和升高的外延源极和漏极区域的形成允许晶体管性能的进一步改善和诸如漏极引起的栅极降低（DIBL）和特征亚阈值斜率的控制的短沟道效应的减少。 可以通过先进的过程控制辅助，改变栅极凹槽以使沟道相对于掺杂物分布形成不同的深度。 部分凹入的栅极具有最初形成为与栅极的三侧接触的相关联的高k栅极电介质。 随后去除高k侧壁和置换较低k氮化硅密封剂降低了栅极和源极和漏极区域之间的电容。

公开(公告)号：US09099570B2

公开(公告)日：2015-08-04

申请号：US14097556

申请日：2013-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/092 ,  H01L21/84 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/76205 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: On a substrate formed of a first semiconductor material, a first overlying layer formed of a second semiconductor material is deposited. A second overlying layer formed of a third semiconductor material is deposited over the first overlying layer. The first and second overlying layers are patterned to define fins, wherein each fin includes a first region formed of the third material over a second region formed of the second material. An oxide material fills the space between the fins. A thermal oxidation is then performed to convert the second region to a material insulating the first region formed of the third material from the substrate. As an optional step, the second region formed of the second material is horizontally thinned before the oxide material is deposited and the thermal oxidation is performed. Once the fins are formed and insulated from the substrate, conventional FinFET fabrication is performed.

Abstract translation: 在由第一半导体材料形成的衬底上沉积由第二半导体材料形成的第一覆盖层。 由第三半导体材料形成的第二覆盖层沉积在第一覆盖层上。 图案化第一和第二覆盖层以限定翅片，其中每个翅片包括在由第二材料形成的第二区域上由第三材料形成的第一区域。 氧化物填充翅片之间的空间。 然后进行热氧化以将第二区域转换为将由第三材料形成的第一区域与衬底绝缘的材料。 作为可选步骤，在沉积氧化物材料并进行热氧化之前，由第二材料形成的第二区域被水平地薄化。 一旦翅片形成并与衬底绝缘，就进行常规的FinFET制造。

公开(公告)号：US09082625B2

公开(公告)日：2015-07-14

申请号：US14102873

申请日：2013-12-11

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Yiheng Xu ,  John Zhang

IPC: B44C1/22 ,  H01L21/033 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/0337 ,  B81C1/0046 ,  G03F7/0002 ,  H01L21/31144

Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.

Abstract translation: 本发明的实施例提供一种形成装置图案的方法。 该方法包括定义要在设备层中创建的设备图案; 在器件层的顶部上形成牺牲层; 识别在其高度的位置处具有表示装置图案的水平横截面形状的压印模具; 将压印模均匀地推入牺牲层，直到至少压印模具的位置达到被压印模推送的牺牲层内的水平面; 将所述压印模具远离所述牺牲层移除; 在由牺牲层中的压印模制成的凹部中形成硬掩模，硬掩模具有表示装置图案的图案; 并将硬掩模的图案转移到器件层的下方。

公开(公告)号：US20150162278A1

公开(公告)日：2015-06-11

申请号：US14098346

申请日：2013-12-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。