公开(公告)号：US07232758B2

公开(公告)日：2007-06-19

申请号：US10710622

申请日：2004-07-26

Applicant: Tai-Yuan Chen

Inventor： Tai-Yuan Chen

IPC: H01L21/302

CPC classification number: H01L22/20 ,  G03F7/70633 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of correcting a lithographic process is provided. A physical vapor deposition process (PVD) is performed to deposit a film on a wafer. The asymmetrical deposition of the film on the sidewalls of an opening is related to the change of target consumption in the PVD process. Therefore, the positional shift in an overlay mark may change each time. However, a formula relating target consumption with the degree of positional shift can be derived. The formula is recorded by a controller system. A compensation value can be obtained from the controller system and fed back in a subsequent lithographic process. Thereafter, a photoresist layer is formed on the film and a lithographic process is performed to pattern the photoresist. Since the compensation value can be fed back in the lithographic process via the controller system to correct for the positional shift in the overlay mark resulting from target consumption in the PVD process, errors in measuring the overlay mark can be reduced.

Abstract translation: 提供了一种校正光刻工艺的方法。 进行物理气相沉积工艺（PVD）以在薄片上沉积薄膜。 膜在开口侧壁上的不对称沉积与PVD工艺中目标消耗的变化有关。 因此，覆盖标记中的位置偏移可以每次改变。 然而，可以导出将目标消耗与位置偏移程度相关联的公式。 公式由控制器系统记录。 可以从控制器系统获得补偿值，并在随后的光刻过程中反馈。 此后，在膜上形成光致抗蚀剂层，并执行光刻工艺以对光致抗蚀剂进行图案化。 由于补偿值可以经由控制器系统在光刻处理中反馈，以校正由PVD过程中的目标消耗导致的覆盖标记中的位置偏移，所以可以减少测量重叠标记的误差。

公开(公告)号：US07224637B2

公开(公告)日：2007-05-29

申请号：US10948554

申请日：2004-09-23

Applicant: Jon Allan Faue

Inventor： Jon Allan Faue

IPC: G11C8/18

CPC classification number: G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A clock generator is provided that is compatible with both DDR1 and DDR2 applications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A circuit block within the clock generator detects when a read or write is active and initiates a YCLK signal on the next falling edge of the internal clock. Two separate mechanisms are used for determining when to terminate the YCLK. One mechanism is a timer path and the other is a path determined by DDR1 and DDR2 control signals. The timer path is strictly time based and is the same for DDR1 and DDR2 parts or modes of operation. The other signal path is different for DDR1 and DDR2 operating modes. A DDR1 control signal turns off YCLK at the next rising edge of the internal clock, and a DDR2 control signal turns off YCLK at the next falling edge of the internal clock.

Abstract translation: 提供与DDR 1和DDR 2应用兼容的时钟发生器。 即使主芯片时钟始终运行，内部YCLK信号仅在集成电路存储器上发生有效读取或写入时导通。 时钟发生器内的一个电路块检测读或写何时有效，并在内部时钟的下一个下降沿启动YCLK信号。 使用两个单独的机制来确定何时终止YCLK。 一种机制是定时器路径，另一种是由DDR 1和DDR 2控制信号确定的路径。 定时器路径是基于时间的，对于DDR 1和DDR 2部件或操作模式是相同的。 对于DDR 1和DDR 2操作模式，其他信号路径不同。 DDR1控制信号在内部时钟的下一个上升沿关闭YCLK，DDR2控制信号在内部时钟的下一个下降沿关闭YCLK。

公开(公告)号：US07214585B2

公开(公告)日：2007-05-08

申请号：US10440500

申请日：2003-05-16

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11529

Abstract: A widened contact area (170X) of a conductive feature (170) is formed by means of self-alignment between an edge (170E2) of the conductive feature and an edge (140E) of another feature (140). The other feature (“first feature”) is formed from a first layer, and the conductive feature is formed from a second layer overlying the first layer. The edge (170E2) of the conductive feature is shaped to provide a widened contact area. This shaping is achieved in a self-aligned manner by shaping the corresponding edge (140E) of the first feature.

Abstract translation: 通过在导电特征的边缘（170E2）与另一特征（140）的边缘（140E）之间的自对准，形成导电特征（170）的加宽的接触区域（170×）。 另一特征（“第一特征”）由第一层形成，并且导电特征由覆盖第一层的第二层形成。 导电特征的边缘（170E 2）成形为提供加宽的接触面积。 通过使第一特征的对应边缘（140E）成形，以自对准的方式实现该成形。

公开(公告)号：US07208127B2

公开(公告)日：2007-04-24

申请号：US10779634

申请日：2004-02-18

Applicant: Cheng-ta Wu ,  Chang-Cheng Chen ,  Chun-Chi Chen

Inventor： Cheng-ta Wu ,  Chang-Cheng Chen ,  Chun-Chi Chen

IPC: B01D47/00

CPC classification number: B01D53/34 ,  B01D45/08 ,  B01D53/74 ,  B01J8/0065 ,  B01J12/00

Abstract: A system for processing residual gas that includes a chamber having at least one baffle for increasing gas flow path, a residual gas inlet mechanism connected to the chamber for supplying residual gas to the chamber, at least one first gas inlet mechanism connected to the chamber for supplying inert gas to the chamber, at least one second gas inlet mechanism connected to the chamber for supplying a reactive gas to the chamber, and a gas outlet mechanism for connected to the chamber for outputting mixed gases from mixing the residual gas, inert gas and reactive gas and non-reacted residual gas, inert gas and reactive gas.

Abstract translation: 一种用于处理残余气体的系统，其包括具有用于增加气体流路的至少一个挡板的室，连接到所述室的残余气体入口机构，用于向所述室供应残余气体;至少一个连接到所述室的第一气体入口机构， 向所述室供应惰性气体，连接到所述室的至少一个第二气体入口机构用于向所述室供应反应性气体;以及气体出口机构，用于连接到所述室，用于从混合残余气体，惰性气体和 反应气体和未反应的残留气体，惰性气体和反应气体。

公开(公告)号：US07163858B2

公开(公告)日：2007-01-16

申请号：US10904479

申请日：2004-11-12

Applicant: Chao-Hsi Chung

Inventor： Chao-Hsi Chung

IPC: H01L21/8242 ,  H01L21/336

CPC classification number: H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

Abstract: A method of fabrication deep trench capacitors includes forming a plurality of deep trenches in a substrate. A bottom electrode is formed in the substrate surrounding the bottom of each deep trench. A capacitor dielectric layer and a first conductive layer are formed at the bottom of each deep trench. A collar oxide layer is formed on the sidewall of the deep trench exposed by the first conductive layer. A second conductive layer fills each deep trench. An opening is formed in a region predetermined for an isolation structure between adjacent deep trenches, wherein the depth of the opening is greater than that of the isolation structure. An isolation layer is filled in the opening.

Abstract translation: 制造深沟槽电容器的方法包括在衬底中形成多个深沟槽。 底部电极形成在每个深沟槽的底部周围的基板中。 在每个深沟槽的底部形成电容器电介质层和第一导电层。 在由第一导电层暴露的深沟槽的侧壁上形成环状氧化物层。 第二导电层填充每个深沟槽。 在相邻深沟槽之间的隔离结构预定的区域中形成开口，其中开口的深度大于隔离结构的深度。 隔离层填充在开口中。

公开(公告)号：US20070010057A1

公开(公告)日：2007-01-11

申请号：US11531954

申请日：2006-09-14

Applicant: Ming TANG

Inventor： Ming TANG

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11553 ,  H01L29/7885

Abstract: A flash memory structure comprises a semiconductor substrate, a source region, a drain region, a first insulating dielectric layer, a floating gate, a second insulating dielectric layer, and a control gate. The semiconductor substrate has a first top surface and a second top surface that is lower than the first top surface. The source region and the drain region are respectively in the second top surface and the first top surface of the semiconductor substrate, and the semiconductor substrate connecting the source region and the drain region is a vertical channel region. The whole channel region is covered by the first insulating dielectric layer, the floating gate, the second insulating dielectric layer, and the control gate in turn.

Abstract translation: 闪存结构包括半导体衬底，源极区，漏极区，第一绝缘介电层，浮栅，第二绝缘介质层和控制栅。 半导体衬底具有比第一顶表面低的第一顶表面和第二顶表面。 源极区域和漏极区域分别位于半导体衬底的第二顶表面和第一顶表面中，并且连接源极区域和漏极区域的半导体衬底是垂直沟道区域。 整个通道区域依次由第一绝缘介电层，浮置栅极，第二绝缘介电层和控制栅极覆盖。

公开(公告)号：US20070004136A1

公开(公告)日：2007-01-04

申请号：US11174081

申请日：2005-06-30

Applicant: Zhong Dong ,  Tai-Peng Lee

Inventor： Zhong Dong ,  Tai-Peng Lee

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/76

CPC classification number: H01L21/823481 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521

Abstract: Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon oxide liner (150.2) incorporating chlorine is deposited by CVD over the first liner (150.1), and then a third liner (150.3) is thermally grown. The chlorine concentration in the second liner (150.2) and the thickness of the three liners (150.1, 150.2, 150.3) are controlled to improve the corner rounding without consuming too much of the active areas (140).

Abstract translation: 在衬底隔离沟槽（134）的蚀刻之前，将氯结合到在硅衬底（120）上形成的衬垫氧化物（110）中。 当在沟槽表面上热生长氧化硅衬垫（150.1）时，氯增强了沟槽的顶角（140℃）的倒圆。 通过CVD在第一衬垫（150.1）上沉积掺入氯的第二氧化硅衬垫（150.2），然后热生长第三衬里（150.3）。 控制第二衬套（150.2）中的氯浓度和三个衬垫（150.1,150.2,150.3）的厚度以改善拐角四舍五入，而不消耗太多的有效区域（140）。

公开(公告)号：US20060255388A1

公开(公告)日：2006-11-16

申请号：US11125676

申请日：2005-05-10

Applicant: Yueh-Chuan Lee ,  Ming-Sheng Tung

Inventor： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC: H01L29/772 ,  H01L27/108 ,  H01L21/8242 ,  H01L21/8232

CPC classification number: H01L29/945 ,  H01L27/1087

Abstract: A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.

Abstract translation: 形成沟槽电容器的方法包括：去除衬底的一部分以在衬底内形成沟槽; 在衬底内的掩埋隔离层处形成; 在所述衬底中至少在围绕所述沟槽的下部的区域中在所述沟槽电容器中形成第一电极; 形成沟槽电容器的电介质层; 以及在所述沟槽中形成所述沟槽电容器的第二电极。 掩埋隔离层与沟槽相交并且具有一个或多个间隙，用于在掩埋隔离层之上的第一衬底区域和掩埋隔离层下面的第二衬底区域之间提供身体接触。

公开(公告)号：US07127595B1

公开(公告)日：2006-10-24

申请号：US09505414

申请日：2000-02-16

Applicant: Dayin Gou

Inventor： Dayin Gou

IPC: G06F7/24

CPC classification number: G06F7/768

Abstract: A method and system of configuring an array of data is disclosed. The method and system comprise generating an array of data an order and reconfiguring the array of data into a plurality sub arrays of data, the plurality of sub arrays of data being in a desired order. By utilizing the method and system in accordance with the present invention, a converted data array can be processed in a parallel fashion thereby increasing the overall processing speed of the computer system. The present invention has particular utility when converting data either from a bit reverse order to a natural order or from a natural order to a bit reverse order. In accordance with the present invention, the array of data is reconfigured utilizing a swap operation to allow for conversion of the data array from either a bit reverse order to a natural order or from a natural order to a bit reversed order.

Abstract translation: 公开了一种配置数据阵列的方法和系统。 所述方法和系统包括生成数据阵列的顺序并且将所述数据阵列重新配置成多个子数据子阵列，所述多个数据子阵列处于所需的顺序。 通过利用根据本发明的方法和系统，可以并行处理转换的数据阵列，从而增加计算机系统的整体处理速度。 本发明在将数据从位逆序转换为自然次序或从自然次序转换为位相反顺序时具有特别的用途。 根据本发明，使用交换操作来重新配置数据阵列，以允许将数据阵列从位相反顺序转换为自然次序，或从自然次序转换为位反转顺序。

公开(公告)号：US07122415B2

公开(公告)日：2006-10-17

申请号：US10243379

申请日：2002-09-12

Applicant: Chuck Jang ,  Zhong Dong ,  Vei-Han Chan ,  Ching-Hwa Chen

Inventor： Chuck Jang ,  Zhong Dong ,  Vei-Han Chan ,  Ching-Hwa Chen

IPC: H01L21/8238

CPC classification number: H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/28211 ,  H01L21/28273 ,  H01L21/3162 ,  H01L21/31683 ,  H01L29/511

Abstract: Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.

Abstract translation: 通过原子层沉积沉积氧化铝以形成用于非易失性存储器件的多晶硅介电层的高k电介质。 增加的电容耦合可以允许在浮动栅极和控制栅极之间使用较厚的氧化物层，从而提高根据本发明制造的存储器单元的可靠性和更长寿命。